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T7264 u-interface 2b1q transceiver data sheet april 1998 features n u-interface 2b1q transceiver ?range over 18 kft on 26 awg ?isdn basic-rate 2b+d ?full-duplex, 2-wire operation ?2b1q four-level line code ?conforms to ansi north american standard t1.601-1992 ?supports nt quiet mode and insertion loss test mode for maintenance n k2 interface ?2b+d data ?512 kbits/s tdm interface ?frame and superframe markers ?embedded operations channel (eoc) ?u-interface m bits and crc results ?device control and status n other ?single +5 v ( 5%) supply ??0 c to +85 c ?44-pin plcc n power consumption ?operating 275 mw typical ?idle mode 30 mw typical n analog front end ?on-chip line driver for 2.5 v pulses ?on-chip balance network ?sigma-delta a/d converter ?internal 15.36 mhz crystal oscillator ?supports 15.36 mhz external clock input n digital signal processor ?digital timing recovery (pull range 250 ppm) ?echo cancellation (linear and nonlinear) ?accommodates distortion from bridged taps ?scrambling/descrambling ?crc calculations ?selectable lt or nt operation ?start-up sequencing with timers ?activation/deactivation support ?cold start in 3.5 seconds (typical) ?warm start in 200 ms (typical) ?u-frame formatting and decoding description the lucent technologies microelectronics group T7264 u-interface 2b1q transceiver integrated cir- cuit provides full-duplex, basic-rate (2b+d) integrated services digital network (isdn) communications on a 2-wire digital subscriber loop at either the lt or nt and conforms to the ansi north american standard t1.601-1992. the single +5 v cmos device is pack- aged in a 44-pin plastic leaded chip carrier (plcc). 5-5161 figure 1. T7264 simpli?d block diagram 2-wire 2b1q u-interface line driver a/d echo canceler balance network + ? scrambler descram. signal detect k2 bus format, decode agc k2 xtal osc. 15.36 mhz dec 2b1q encoder dfe dig. pll T7264
table of contents contents page contents page 2 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver features .......................................................................... 1 description ....................................................................... 1 pin information ................................................................ 3 functional overview ......................................................... 6 device interface and connections.................................... 7 analog device interface ................................................ 7 power supply connections............................................ 8 clock operation ............................................................. 8 reset operation............................................................. 8 reset sequences and clock synchronization ............ 8 reset time.................................................................. 9 idle mode ..................................................................... 10 nt maintenance .......................................................... 10 k2 interface description ................................................ 11 k2 nt and lt timing sources..................................... 12 k2 bits description ...................................................... 13 k2 bit levels ................................................................ 20 u-interface description .................................................. 21 k2 functional description .............................................. 22 k2 framing bits ........................................................... 23 k2 eoc and loopback response timing .................... 24 k2 device status and control bits............................... 25 the adea bit ................................................................ 26 the nebe, febe, rfebe, and ccrc bits ............................ 27 nt or lt operation ........................................................ 28 minimal example ............................................................ 29 activation and the k2 interface ...................................... 30 priority ......................................................................... 31 applications .................................................................... 32 absolute maximum ratings ........................................... 34 handling precautions ..................................................... 34 recommended operating conditions ............................ 34 electrical characteristics ............................................... 35 loop-range performance characteristics ..................... 36 timing characteristics ................................................... 37 switching test input/output waveform .......................... 38 outline diagram ............................................................. 39 ordering information ...................................................... 39 appendix a. questions and answers ............................ 40 introduction .................................................................. 40 u-interface ................................................................... 40 k2 interface ................................................................ 46 miscellaneous ............................................................. 49 appendix b. differences between the t-7264- - -ml, t-7264- - -ml2 and t-7264a- -ml devices ................... 53 technology................................................................... 53 standard ...................................................................... 53 list of figures figure 1. T7264 simpli?d block diagram ....................... 1 figure 2. pin diagram ...................................................... 3 figure 3. quat example ................................................... 6 figure 4. line interface and protection ............................ 7 figure 5. recommended power supply connections .................................................................. 8 figure 6. reset waveform normal operation ............... 9 figure 7. reset timing for synchronized clocks .......... 9 figure 8. k2 interface timing ......................................... 11 figure 9. k2 octets ........................................................11 figure 10. k2 interface lt and nt .................................12 figure 11. k2 interface frame format ...........................14 figure 12. u-interface frame and superframe ..............21 figure 13. u-interface superframe bit groups ..............21 figure 14. k2 octet description .....................................22 figure 15. k2 functional description .............................22 figure 16. k2-to-u mapping ...........................................23 figure 17. u-to-k2 mapping ...........................................24 figure 18. k2 response timing .....................................24 figure 19. T7264 nebe/febe/crc block diagram .............28 figure 20. use of rfebe in a multilink conguration .......28 figure 21. state sequence for dsl transceiver start-up .......................................................................32 figure 22. loop application ...........................................33 figure 23. 2-wire terminal application ..........................33 figure 24. digital pair gain application .........................33 figure 25. timing diagram referenced to f ..................37 figure 26. timing diagram referenced to c ..................37 figure 27. reset timing diagram ................................38 figure 28. switching test waveform ..............................38 list of tables table 1. pin functions ......................................................3 table 2. pin descriptions ..................................................4 table 3. clock con?uration ............................................6 table 4. k2 interface serial data bit map ......................13 table 5. b1, b2, d, and s1 octets (overview) ...............15 table 6. b1, b2, d, and s1 octets (functions) ...............15 table 7. um1 and um2 octets?oc bits (overview) ....16 table 8. um1 and um2 octets?oc bits (functions) ....16 table 9. um2 and um3 octet?cs bits (overview) ....17 table 10. um2 and um3 octet?cs bits (functions) ..17 table 11. ds octet (overview)?evice status .............18 table 12. ds octet (functions)?evice status ............18 table 13. dc octet (overview) ......................................19 table 14. dc octet (functions) ......................................19 table 15. k2 data out (do) bit levels ...........................20 table 16. k2 device control (dc) bit levels ..................20 table 17. u-interface bit assignment .............................22 table 18. dc octet description (control) .......................25 table 19. ds octet description (status) ........................25 table 20. adea, ldea, and dea function .........................26 table 21. mode0 pin functionality ...............................28 table 22. minimal implementation ..................................29 table 23. de?itions of signals during start-up ............31 table 24. power consumption .......................................35 table 25. performance ratings ......................................35 table 26. crystal characteristics: fundamental mode crystal ...............................................................35 table 27. internal pll characteristics ...........................36 table 28. digital dc characteristics (over operating ranges) ......................................................................36 table 29. clock timing ...................................................37 table 30. mtc requirements and characteristics (lt mode) ....................................................................38 table 31. reset timing ................................................ 38
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 3 pin information the u transceiver consists of a single chip composed of an analog front end (which performs the line interfacing and data conversion functions) and a digital signal processor (which performs the algorithm-speci? signal pro- cessing, control, and access functions). 5-5804(f) notes: c = crystal oscillator pins. a = analog pins. figure 2. pin diagram table 1. pin functions device pin function type number of pins +5 v power & ground (v dd , gnd) power 14 analog line interface (hp, hn, lop, lon) analog 4 voltage reference (vrp, vrn, vcm) analog 3 receiver to a/d converter (sdinn, sdinp) analog 2 clock related (x1, x2, ckout, cksel, mclk, rclken) digital 6 k2 interface connection (mtc, c, di, do, f) digital 5 device status & control (ffc , highz , iloss , mode0, mode1, osync , reset ) digital 7 do not connect nc 3 total ?4 7 9 10 11 12 13 14 15 8 iloss ffc reset mode0 gnd d mode1 nc nc nc 16 17 osync v ddd sdinn sdinp v dda hp gnd a lon v dda lop hn vrn vrp do f v ddd c di mtc gnd d rclken v dda gnd a gnd a x1 gnd o v ddo x2 ckout gnd d mclk cksel highz gnd d vcm 6 4 3 2 1 44 43 42 54140 39 37 36 35 34 33 32 31 38 30 29 18 20 21 22 23 24 25 26 19 27 28 a a a a a a a a a a a a a a c c c c a T7264 k2 interface
4 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver pin information (continued) table 2. pin descriptions pin symbol type name/function 1 di i k2 transmit data input. serial data input passing transmit data across k2 in- terface at 512 kbits/s. latched on falling edge of c clock. 2 mtc i master timing clock. 8 khz clock input. in lt mode (mode0 = 1), all clocks except ckout in the 15.36 mhz and 7.68 mhz modes are locked to this input clock. in the nt mode (mode0 = 0), this input is not used. 3 c o 512 kbits/s k2 bit clock output. synchronized to f. defines k2 bit period (ris- ing edge to rising edge). 4 do o k2 receive data output. serial data output passing receive data across k2 in- terface at 512 kbits/s. changes on the rising edge of c clock. 5 f o 8 khz clock output. defines k2 frame (rising edge to rising edge). in lt mode (mode0 = 1), this clock is locked to mtc at 0 phase shift with 65 ns of jitter (for jitter-free mtc). in nt mode (mode0 = 0), this clock is derived from the u-interface signal. 6, 17 v ddd p +5 v supply for digital circuits. internally connected together. 7 reset i reset (active-low). asynchronous schmitt trigger input. this pin maintains the transceiver in reset indefinitely without the need to access the k2 interface. it must be held low for three consecutive f clock periods for active or idle mode or 1.5 ms after power on. after power-on reset or idle mode reset, an additional 1.0 ms is required before the device is fully functional. reset overrides all other transceiver control signals, halts loop transmission, clears the transceiver adap- tive filter coefficients, and resets the phase-locked loop. after a reset, the next activation is a cold start. unlike afrst (software reset via the k2 interface), when this pin is held low, synchronization is lost between f and mtc (lt). after this pin goes high, f and mtc regain synchronization. all output clocks remain func- tional during reset. 8 ffc i freeze frequency control (active-low). asynchronous input. freeze the clock frequency control (i.e., the internal state variables of the timing recovery remain constant). this control is operative in both lt and nt modes. this pin is latched on the rising edge of every rclken. 9 iloss i insertion loss test (active-low). nt only. when enabled, the transmitter continuously transmits the sequence sn1. the receiver remains reset. the transceiver performs a reset when this pin returns to its inactive state. iloss is latched on the rising edge of f. leave this pin unconnected or tied to v dd in lt mode. 10, 11 mode[0:1] i mode 0 and 1. two-pin field selecting chip mode: mode0 action 0 configure for chip being used on the nt end of loop. 1 configure for chip being used on the lt end of loop. mode1 action 0 disables autoreporting of nebe to febe. 1 enables autoreporting of nebe to febe. 12, 22, 27, 44 gnd d p ground supply for digital circuits. internally connected together.
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 5 pin information (continued) table 2. pin descriptions (continued) pin symbol type name/function 13, 14, 15 nc no connect. these pins are connected to internal nodes of the device. make no con- nection to them. 16 osync o out of sync (active-low). indicates that framing on the loop signal has not been ac- quired (or has been lost). equivalent to the k2 interface oof bit in the ds octet. can sink or source 1.6 ma to drive a low-current external led. clocked out on the rising edge of c. 18 v ddo p/i +5 v supply for the crystal oscillator. ground when driving mclk with an external 15.36 mhz clock. 19 gnd o p ground supply for oscillator. 20 x1 i connection #1 for a 15.36 mhz crystal. 21 x2 i connection #2 for a 15.36 mhz crystal. 23 ckout o clock output. see table 3. 24 mclk i master clock. see table 3. 25 cksel i clock select. see table 3. 26 highz i high impedance (active-low). causes all digital outputs to become 3-stated. 28 vcm common-mode voltage reference for the analog circuits. connect via a 0.1 m f capacitor to gnd a as close to this pin and pin 34 as possible. 29 vrp positive voltage reference for the analog circuits. connect via a 0.1 m f capacitor to gnd a as close to this pin and pin 34 as possible. 30 vrn negative voltage reference for the analog circuits. connect via a 0.1 m f capacitor to gnd a as close to this pin and pin 34 as possible. 31 hn i hybrid network connection, negative side. connect directly to the negative side of the transformer. 32 lop o line driver output terminal, positive side. connect to the positive side of the trans- former. 33, 39, 42 v dda p +5 v supply for analog circuits. 34, 40, 41 gnd a p ground supply for analog circuits. 35 lon o line driver output terminal, negative side. connect to the negative side of the transformer. 36 hp i hybrid network connection, positive side. connect directly to the positive side of the transformer. 37 sdinn i sigma-delta a/d converter input, negative side. connect via an 820 pf 5% capacitor to sdnip. 38 sdinp i sigma-delta a/d converter input, positive side. connect via an 820 pf 5% capacitor to sdnin. 43 rclken o 80 khz receive baud clock. defines receive baud period (rising edge to rising edge).
6 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver pin information (continued) table 3. clock con?uration * the 10.24 mhz ckout is high for one-half of a 15.36 mhz period and low for one 15.36 mhz period. to compensate for the difference be- tween the phase-locked and free-run frequencies, one-half 15.36 mhz clock periods are occasionally either removed from or added to the low time of the 10.24 mhz period. functional overview 5-5162f figure 3. quat example v ddo mclk cksel ckout * +5 v +5 v +5 v +5 v 0 0 1 1 0 1 0 1 15.36 mhz (free-running) 10.24 mhz (phase-locked) 7.68 mhz (free-running) 3-stated (default) 0 v 0 v 15.36 mhz 15.36 mhz 0 1 15.36 mhz (free-running) 3-stated ? 01 +3 10 +1 11 ? 00 ? 00 +1 11 +3 10 ? 00 ? 01 ? 01 +1 11 ? 01 ? 00 +3 10 +3 10 ? 01 +1 11 +3 +1 ? ? quat bits the T7264 chip conforms to the t1.601 ansi north american 1992 standard for 2b1q line encoding. the 2b1q line code provides a four-level pulse amplitude modulation code with no redundancy. data is grouped into pairs of bits for conversion to quaternary (quat) symbols. figure 3 above shows an example of this cod- ing method. the analog front end provides the 2b1q line coder (d/a conversion), pulse shaper, line driver, ?st-order line balance network, crystal oscillator clock genera- tion, and sigma-delta a/d conversion. the line driver provides pulses which allow the 2.5 v template of the t1.601 speci?ation to be met when connected to the proper transformer and interface circuitry. the a/d con- verter is implemented using a double-loop, sigma-delta modulator. a crystal oscillator provides the 15.36 mhz master clock for the chip. an on-chip, digital phase-locked loop provides the ability to synchronize the chip clock to the system clock in the lt or to the line clock in the nt. provisions are made for using either an on-chip crystal oscillator with an external crystal, or using an external clock source. the T7264 takes input at the k2 interface and formats this information for the u-interface through a scram- bling algorithm and the addition of synchronization bits for u framing. this data is then transferred to the 2b1q encoder for transmission over the u loop. signals com- ing from the u loop are ?st passed through the sigma- delta a/d converter and then sent for extensive signal processing. the T7264 provides decimation of the sigma-delta output (dec), linear and nonlinear echo cancellation, automatic gain control (agc), signal detection, decision feedback equalization (dfe), timing recovery (tr), descrambling, line-code polarity detec- tion, and rate adaption for output onto the k2 interface. the dfe circuit provides the functionality necessary for proper operation on subscriber loops with bridged taps.
lucent technologies inc. 7 data sheet april 1998 T7264 u-interface 2b1q transceiver functional overview (continued) the device provides rapid cold start and warm start op- eration. from a cold start, the device is typically opera- tional within 3.5 s. the device supports activation/ deactivation, and, when properly deactivated, it stores the adaptive filter coefficients such that upon the next activation request, a faster warm start is possible. a warm start typically requires 200 ms for the device to be- come operational. the T7264 has an on-chip activation/deactivation state machine and timers, and automatically moves from state t0 to t7 (as specified in the t1.601 standard) dur- ing activation. this simplifies the implementation of the t1.601 (appendix c) state table. the signals from the device control and status octets on the k2 interface pro- vide the control necessary to complete the state table. the activation/deactivation process is controlled over the k2 interface. the T7264 has a low-power mode which it automatically enters when it is in the idle state. the idle state occurs after deactivation, loss of sync on the u-interface, or re- leasing reset. in the low-power mode, power consump- tion is typically 30 mw. device interface and connections the T7264 transceiver allows systems to meet the loop-range requirements of ansi standard t1.601 when the transceiver is used with the proper peripheral circuitry. devices achieve better than 10 ? bit error rate over 18 kft of 26 awg loop cable. analog device interface proper line termination is required, utilizing appropriate interface components, to meet the 2.5 v pulse tem- plate. the output of the T7264 should first pass through a pair of 16.9 w resistors and into a 1.5:1 ratio trans- former, such as the lucent 2754h (or the short-lead version 2754h2). the output of the transformer is cou- pled through a 1.0 m f capacitor, is passed through a pair of 16.9 w resistors, and then drives the 135 w line. surge protection circuitry is necessary on each side of the transformer when the u loop is external to a build- ing. the protection between the 16.9 w resistors and the transformer should be a lucent 521a surge protec- tor or equivalent. a relay may be needed to disconnect the loop plant for local loopback testing. figure 4 shows a recommended circuit for interfacing the T7264 to the line; however, the specific interface is system depen- dent. 5-5803fa note: 3000 pf 1% capacitors from hp and hn to gnd a may improve operation of the tone decoder in the presence of interfering common- mode signals. figure 4. line interface and protection 0.1 m f gnd a T7264 lon hn hp lop sdinp sdinn vrp vrcm vrn gnd a 1 9 7 5 521a surge protection 1.5:1 surge protection 16.9 w 7% loopback relay 10 6 2754h 16.9 w 7% 16.9 w 1% 16.9 w 1% 820 pf 5% 1.0 m f 29 28 30 24 37 38 31 35 32 36 dc remote power source lucent 701c
8 8 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver device interface and connections (continued) power supply connections figure 5 shows a recommended power supply connec- tion. c is a 10 m f capacitor. each pair of power and ground pins should be decoupled with 0.1 m f and 1.0 m f capacitors. each of the three leads (vcm, vrp, and vrn) associated with the voltage reference should be decoupled with 0.1 m f capacitors. place the capaci- tors as close as possible to the power or reference and ground pins which they decouple. clock operation the master clock for the T7264 may either be internally generated by the on-chip crystal oscillator or supplied by the user via the mclk pin. in the latter case, v ddo must be grounded. in the lt mode, an on-chip digital phase-locked loop phase locks the f clock to the exter- nally supplied mtc clock, unless ffc is active-low. in nt mode, f synchronizes to the signal received from the lt through the u-interface. if the on-chip crystal os- cillator is used, the crystal must conform to the require- ments given in table 26. reset operation the T7264 can be reset via the k2 interface (issuing afrst for three consecutive k2 frames) or via hardware (reset ). the only difference between these two resets is that, in the lt mode, the timing recovery filter is reset only by a hardware reset. the reset pin can be used to hold the transceiver in reset indefinitely. if a hardware reset is used when the chip is being powered up, reset must be held low for 1.5 ms; however, if the chip is already powered up, then holding reset low for three k2 frames is sufficient. the reset state is terminated, and the chip enters idle mode on the k2 frame following the end of the reset sig- nal. reset sequences and clock synchronization in normal use, a power-on reset can be obtained by connecting a capacitor to the reset pin. the internal pull-up resistor, acting with an on-chip schmitt trigger on this pin, can be used to reset the chip. in this case, the reset waveform is shown in figure 6. when using this reset procedure, the various clocks generated by the transceiver are not synchronized. however, during testing, it can be useful to initialize all the counters of the clock generator so that the various clocks generated by the transceiver can be synchro- nized to the test equipment. the reset pin can ac- complish this by applying the sequence shown in figure 7. furthermore, the reset pin transitions should align with falling edges of mclk. if the internal crystal oscil- lator is used, this can be accomplished by configuring ckout for 15.36 mhz and ensuring that reset tran- sitions align with the falling edge of ckout. the user should be aware, however, that if this clock synchroni- zation reset sequence is used after a period of normal operation, the phase of the clocks generated by the T7264 (such as f, rclken, c, ckout, etc.) may sud- denly change as a result of the clock resynchronization. 5-5164a figure 5. recommended power supply connections c +5 v sysgnd v ddd 6, 17, 18 gnd d 12, 22, 27, 44 digital analog gnd o to v ddd (internal vcxo) or gnd d (external mclk) vcm, 28 vrp, 29 vrn, 30 0.1 m f 33, 39, 42 gnd a v ddo v dda 0.1 m f 0.1 m f (34, 40, 41) 19
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 9 device interface and connections (continued) reset time reset time depends on the conditions under which the chip is reset. there are three cases to consider: n when the chip is initially powered on, the reset pin must be held low (below 0.5 v) for 1.5 ms. this allows 1.0 ms for the oscillator start-up and 0.5 ms for the digital reset process. an additional 1.0 ms is needed to allow the analog circuitry to fully power up before the chip becomes fully functional. n when the chip is in the idle mode, a software or hardware reset, applied for a minimum of three k2 frames, starts the reset process. as before, the analog circuitry requires an additional 1.0 ms before the chip becomes fully functional. n if the chip is already fully powered up and functional, a software or hardware reset, applied for a minimum of three k2 frames, is suf?ient to complete the reset process. when the chip is in the reset state, the output of the line driver is at 0 v and the transmit data is also 0 v. 5-5165a figure 6. reset waveform normal operation 5-5166a figure 7. reset timing for synchronized clocks reset pin internal reset (after schmitt trigger) t t device reaches power-on mode (fully functional) 4.75 v power supply voltage 1.5 ms min 1.0 ms 0 0 1 4.75 v power supply voltage reset pin 1 normal reset as in figure 6 undefined undefined 1 mclk period 2 mclk periods f c 3 2.5 ms 3 3 k2 frames
10 10 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver device interface and connections (continued) idle mode a low-power idle mode is implemented on the T7264 to reduce the power consumption to typically 30 mw when it is not active. all internal coefficients are saved in this idle mode to reduce time for a subsequent start-up. there are three ways that idle mode can be entered: n if the loop is operational, the local deactivation com- mand (ldea) in the lt mode via the k2 interface causes the deactivation procedure speci?d in the ansi standard. at the conclusion of the deactivation procedure, shutdown of the line driver and activation of the tone detector occurs. if no tone is detected within 48 ms, the idle mode is entered. this 48 ms window constitutes the receive reset criteria in the ansi standard. n if a failure condition is encountered (e.g., the loop never comes up), a procedure similar to deactivation is followed. the only difference is the duration of the window, which is set internally by the type of failure condition. n as long as either the afrst (via the k2 interface) or the reset pin is active, the transceiver remains in the powerup reset state. at the cessation of the reset condition, the transceiver changes to the idle state. there are four ways of bringing the device out of the idle mode: n an initiate start-up procedure (istp) command is received via the k2 interface by the device. n a reset (afrst or external reset ) command is received by the device. n a tone is detected by the tone detector. n a command to enter any of the test modes (loopback and insertion loss) is received by the device. internal timing ensures that the digital signal processor blocks do not change state during the idle mode-to- powerup process. in addition, the start-up process has been designed to prevent glitches on the line as the driver powers up. nt maintenance ansi t1.601-1992 defines nt quiet mode operation and an insertion loss measurement, and support for these is available from the T7264. detection of the trig- ger signals is done by other hardware which notifies the system controller, and the system controller then sig- nals the T7264 as needed to do the following: n to enter the quiet mode, the chip is placed in reset. n when an insertion loss measurement is requested, iloss (pin 9) is asserted low. this causes the trans- mitter to continuously send sn1 and places the receiver in reset. when the test is completed or ter- minated, iloss is asserted high and the chip is reset. priority between reset and iloss is described in the priority section of this document (page 31).
lucent technologies inc. 11 data sheet april 1998 T7264 u-interface 2b1q transceiver k2 interface description the k2 interface consists of five pins on the T7264: the data out (do), data in (di), data clock (c), k2 frame sync (f), and master timing clock (mtc). c is a 512 khz output signal for clocking data into and out of the device with 1 bit per clock cycle. f is an 8 khz signal indicating the beginning of a k2 frame. mtc is used in lt mode and must be an 8 khz 32 ppm system clock to meet t1.601 requirements. in lt mode, f is phase-locked to the mtc input through the on-chip digital phase-locked loop. jitter in mtc is tracked by f at frequencies below 0.5 hz. mtc jitter at frequencies higher than 0.5 hz is attenuated by the phase-locked loop (pll). in the nt mode, the f clock is derived from incoming data from the u loop. the first bit of a k2 frame begins simultaneously with the rising edge of f. transitions on do occur following the rising edge of c, and di is latched on the falling edge of c. figure 8 shows the relationship between the c, f, do, and di. the k2 frame consists of eight octets for a total of 64 bits. these bits are transferred synchronously over a 512 khz interface with a frame rate of 8 khz or 125 m s. the major purpose of the k2 interface is to provide 2b+d data transfer between other devices and the chip. in addition, there are framing bits (df), u-interface maintenance and control bits (um), and device control/status bits (dc/ds). 5-5167f figure 8. k2 interface timing 5-5158 figure 9. k2 octets c f do di 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 b1 time slot c f do b1 b2 df um1 um3 ds um2 all 1s di b1 b2 d um1 um3 dc um2 all 1s
12 12 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver k2 interface description (continued) k2 nt and lt timing sources in lt applications, all devices typically derive their tim- ing from the same mtc. additional logic in the lt, such as a t7270, can provide concentration of multiple k2 in- terfaces onto a single higher-speed highway. in a pbx application, the u-interface loops can be used as trunks. if more than one incoming u trunk is to be used, additional circuitry may be needed to provide elastic store, time-slot allocation, and master frame tim- ing to synchronize the k2 interfaces received at each trunk onto a common interface. in nt1 applications, k2 frame timing is also derived from the received 2b1q data on the u loop. a T7264 chip can be connected to an s/t-interface device (such as the t7252a) to form an nt1. figure 10 shows the k2 interface connection in a co application and nt1 appli- cation. for terminal applications, the derived k2 timing could be the source of all timing within the equipment (if only a single u-interface is needed). 5-5169 figure 10. k2 interface lt and nt T7264 mtc f c do di f c di do master timing T7264 mtc f c do di f c di do k2-to- system back- plane logic f c di do s/t t7252a T7264 mtc f c do di v dd 2-wire u- interface nt lt 2-wire u- interface ?? k2-to- system back- plane logic k2 nt1 logic f c di do 4-wire s/t-interface nt lt ?? co switch nt1
lucent technologies inc. 13 data sheet april 1998 T7264 u-interface 2b1q transceiver k2 interface description (continued) k2 bits description table 4 summarizes the k2 interface bits which are common to all con?urations. the k2 frame consists of eight octets of data. the ?st three octets contain the 18 bits of 2b+d data. bits 5? of the third octet contain u frame and superframe timing (df). octet 4 (s1) is reserved for future use and should always be set to 1. octets 5, 6, and 7 are directly mapped to the u-inter- face m (um) maintenance bits which are transparent to the device, except the adea bit. octet 8 is for device status (ds) and device control (dc). these bits must be manipulated according to the t1.601 standard to obtain proper system-level operation. figure 11 describes the four different k2 interface for- mats for do and di at the nt and lt. tables 5?4 de- scribe the position and meaning of the various bits on the k2 interface. tables 15 and 16 show the active logic level for these bits, their value during reset/idle, and their value when the transceiver is operational. table 4. k2 interface serial data bit map bits marked with 1 should always be set to a 1. bits marked as rxx are reserved by t1.601 and should be set to a 1. * items differ dependent upon nt or lt mode. ? don't care. time -----------------------------------------------------------> symbol octet bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 b1 1 b11 b12 b13 b14 b15 b16 b17 b18 b2 2 b21 b22 b23 b24 b25 b26 b27 b28 d 3 d1 d2 1 1 1 1 1 1 df 3 d1 d2 1 1 rsf rf tsf tf s1 4 1 1 1 1 1 1 1 1 um1 5 a1 a2 a3 dm i1 i2 i3 i4 um2 6 i5 i6 i7 i8 act r 1, 5 r 1, 6 * um3 7 r 2, 5 * * * * r 6, 4 * * ds 8 nebe xact ? 1 oof 1 rsksi 1 dc 8 ccrc istp lpbk afrst ldea 1 sksi xpcy
14 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver k2 interface description (continued) 5-5170 figure 11. k2 interface frame format do at nt di b1 b2 d s1 um1 um2 um3 dc do lt b1 b2 df s1 um1 um2 um3 ds b1 b2 df s1 um1 um2 um3 ds di nt b1 b2 d um1 um2 um3 dc 12 345 678 octet di at nt a c t r 1 5 r 1 6 a d e a r 2 5 r f e b e r 3 4 r 4 4 r 5 4 r 6 4 u o a a i b c c r c i s t p l p b k a f r s t l d e a s k s i x p c y a 1 a 2 a 3 d m i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 eoc b1 channel b2 channel d 11111111111111 a 1 a 2 a 3 d m i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 eoc b1 channel b2 channel d 11 r s f r f t s f t f 11111111 a 1 a 2 a 3 d m i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 eoc b1 channel b2 channel d 11111111111111 a c t r 1 5 r 1 6 r 2 5 r 3 4 r 4 4 r 5 4 r 6 4 u o a a i b c c r c i s t p l p b k a f r s t l d e a s k s i x p c y a c t r 1 5 r 1 6 p s 1 r 2 5 r f e b e p s 2 n t m c s o r 6 4 s a i n i b n e b e x a c t o o f r s k s i d e a f e b e 1 a c t r 1 5 r 1 6 p s 1 r 2 5 p s 2 n t m c s o r 6 4 s a i n i b n e b e x a c t o o f r s k s i a 1 a 2 a 3 d m i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 eoc b1 channel b2 channel d 1 1 r s f r f t s f t f 11111111 f e b e 1 11 1 1 11 di at lt do at lt 1 0 o r 1 0 o r s
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 15 k2 interface description (continued) table 5. b1, b2, d, and s1 octets (overview) table 6. b1, b2, d, and s1 octets (functions) octet octet # do/di bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 b1 1 do/di b11 b12 b13 b14 b15 b16 b17 b18 b2 2 do/di b21 b22 b23 b24 b25 b26 b27 b28 d 3 di d1 d2 1 1 1 1 1 1 df 3 do d1 d2 1 1 rsf rf tsf tf s1 4 do/di 1 1 1 1 1 1 1 1 octet bit # symbol name/function b1 1? b11?18 b1 octet. the b1 octet is used for transferring basic access channel b1. b11 is the first bit of the b1 octet sent or received. b2 1? b21?28 b2 octet. the b2 octet is used for transferring basic access channel b2. b21 is the first bit of the b2 octet sent or received. d 1? d1, d2 d octet. the two d-channel bits are transmitted in the first 2 bits of the d octet. d1 is the first bit of the d pair sent or received. df 5 rsf receive superframing. 12.5% duty cycle at an 83.333 hz rate (12 ms). 0?ast 84 k2 frames of the superframe. 0 to 1?arks the first k2 frame of 2b+d data. corresponds to the first 2b+d data of the u superframe. 1?irst 12 k2 frames and during reset state up to point t6 or t7. df 6 rf receive framing. 50% duty cycle at a 666.66 hz rate (1.5 ms). 0?ast six k2 frames of the u frame. 0 to 1?arks every 12th k2 frame of 2b+d data. corresponds to the first 2b+d data of the u frame. 1?irst six k2 frames and during reset state up to point t6 or t7. df 7 tsf transmit superframing. 12.5% duty cycle at an 83.333 hz rate (12 ms). 0?ast 84 k2 frames of the superframe 0 to 1?arks the first k2 frame of 2b+d data. corresponds to the first 2b+d data of the u superframe. 1?irst 12 k2 frames and during reset state up to point t6 or t7. df 8 tf transmit framing. 50% duty cycle at a 666.66 hz rate (1.5 ms). 0?ast six k2 frames of the u frame. 0 to 1?arks every 12th k2 frame of 2b+d data. corresponds to the first 2b+d data of the u frame. 1?irst six k2 frames and during reset state up to point t6 or t7. s1 1? s11?18 s1 octet. all bits of the s1 octet are set to 1.
16 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver k2 interface description (continued) table 7. um1 and um2 octets?oc bits (overview) table 8. um1 and um2 octets?oc bits (functions) additional details on eoc bits can be found in t1.601. octet octet # do/di bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 um1 5 do/di a1 a2 a3 dm i1 i2 i3 i4 um2 6 do/di i5 i6 i7 i8 see next page. octet bit # symbol name/function um1, 2 1?, 1? eoc eoc bits. the eoc bits are passed transparently from the u-interface to the k2 interface and from the k2 to the u-interface. the transceiver maintains the eoc information at the k2 interface until a new block of eoc information is available. um1 1? a1?3 eoc address. 000?t address. 001?t to nt intermediate address. 010?10?t to nt, decrement address and pass on. 001?01?t to lt, increment address and pass on. 111?roadcast address. um1 4 dm data or message indicator. 0?ata. 1?essage. um1, 2 5?, 1? i1?4, i5?8 information. eoc channel message information. 01010000?perate 2b+d loopback. 01010001?perate b1 channel loopback. 01010010?perate b2 channel loopback. 01010011?equest corrupt crc. 01010100?otify of corrupted crc. 11111111?eturn to normal. 00000000?old state. 10101010?nable to comply. refer to t1.601 for codes which are reserved, nonstandard, or internal net- work use.
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 17 k2 interface description (continued) table 9. um2 and um3 octet?cs bits (overview) table 10. um2 and um3 octet?cs bits (functions) octet octet # do/di bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 um2 6 do lt /[di nt ] see previous page. act r 1, 5 r 1, 6 ps1 um2 6 do nt /[di lt ] see previous page. act r 1, 5 r 1, 6 [a]dea um3 7 do lt /[di nt ] r 2, 5 [r]febe ps2 ntm cso r 6, 4 sai nib um3 7 do nt /[di lt ] r 2, 5 [r]febe r 3, 4 r 4, 4 r 5, 4 r 6, 4 uoa aib octet bit # symbol name/function um2 5 act activation. passed transparently from the k2 to the u-interface and from the u to the k2 except during a start-up when it is forced to a 0 on the k2. 0?ending activation. 1?eady to transmit information. um2 6, 7 r x, y reserved bits. passed transparently from the k2 to the u-interface and from the u to the k2. transmit should always be set to a 1. um2 8 ps1 (do lt / di nt ) power status #1. passed transparently from the k2 to the u-interface at the nt and from the u to the k2 at the lt. 0?rimary power out. 1?rimary power is normal. when both ps1 and ps2 are 0, this indicates a dying gasp. um2 8 [a]dea (do nt / di lt ) [and with] deactivate. in lt mode, this bit is used in conjunction with the ldea bit from the k2, then passed to the u-interface as the transmitted dea bit. in nt mode, this bit is passed transparently from the u to the k2 interface. allows deactivation warning to the far-end nt without deactivating the local transceiver. 0?eactivation warning. 1?ormal. um3 1, 6 r x, y reserved bits. passed transparently from the k2 to the u-interface and from the u to the k2 interface. transmit should always be set to a 1. um3 2 [r]febe [receive] far-end block error. if the mode1 = 1, rfebe is anded with nebe and the result is sent out as the u-interface febe bit. if the mode1 = 0, rfebe is passed trans- parently from the k2 (do lt /di nt ) to the u-interface febe bit. for either setting of mode1, the febe bit is passed transparently from the u-interface to the k2 interface. 0?rror indication passed to the originator. 1?o error, or feature is not utilized. um3 3 ps2 (do lt / di nt ) power status #2. passed transparently from the k2 to the u-interface at the nt and from the u to the k2 at the lt. 0?econdary power out. 1?econdary power normal. when both ps1 and ps2 are 0, this indicates a dying gasp. um3 4 ntm (do lt / di nt ) nt test mode. passed transparently from the k2 to the u-interface at the nt and from the u to the k2 at the lt. 0?he nt is currently in a test mode. 1?ormal.
18 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver k2 interface description (continued) table 10. um2 and um3 octet?cs bits (functions) (continued) table 11. ds octet (overview)?evice status table 12. ds octet (functions)?evice status octet bit # symbol name/function um3 5 cso (do lt / di nt ) cold start only. passed transparently from the k2 to the u-interface at the nt and from the u to the k2 at the lt. 0?old and warm start capability. 1?old start only. um3 3, 4, 5 r x, y (do nt /di lt ) reserved bits. passed transparently from the k2 to the u-interface (di lt ) and from the u to the k2 interface (do nt ). transmit should always set to a 1. um3 7 sai (di nt / do lt ) s/t-interface activity indicator. passed transparently from the k2 to the u-inter- face at the nt and from the u to the k2 interface at the lt. 0?o activity at the s/t-interface. 1?ctivity (info1 or info3) at s/t-interface. um3 7 uoa (di lt / do nt ) u-interface only activation. passed transparently from the k2 to the u-interface at the lt and from the u to the k2 interface at the nt. 0?equest s/t deactivation at the nt. 1?llow s/t activation at the nt. um3 8 nib (di nt / do lt ) network indicator bit. passed transparently from the k2 to the u-interface at the nt and from the u to the k2 interface at the lt. reserved for network use. normally set to 1 in customer premises equipment. um3 8 aib (di lt / do nt ) alarm indication bit. passed transparently from the k2 to u-interface at the lt and from the u to the k2 interface at the nt. 0?ailure of intermediate 2b+d transparent element. 1?ransmission path is established between nt and local exchange. octet octet # do/di bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 ds 8 do nebe xact 1 oof 1 rsksi 1 octet bit # symbol name/function ds 1 nebe near-end block error. 0?rc error detected in previously received u frame. 1?ormal. ds 2 xact transceiver active. 0?ransceiver in reset state. 0 to 1?etection of a tone or istp = 0. 1?ransceiver active. 1 to 0?n reset, 480 ms after loss of sync or deactivation. ds 3 undefined. may be either a 1 or a 0. ds 4, 6, 8 reserved. in normal operation, these bits are 1. ds 5 oof out of frame. 0?ut of frame. 1 to 0?nitiates the 480 ms loss of synchronization timer. 1?ormal. ds 7 rsksi reflected system-to-k2. this bit reflects the value of the sksi bit received over the k2 interface.
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 19 k2 interface description (continued) table 13. dc octet (overview) table 14. dc octet (functions) octet octet # do/di bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 dc 8 di ccrc istp lpbk afrst ldea 1 sksi xpcy octet bit # symbol name/function dc 1 ccrc corrupt cyclic redundancy check. this bit is used to corrupt the crc information transmitted by the transceiver to the u-interface. 0?orrupt crc generation as long as bit is low. 1?enerate correct crc (normal). dc 2 istp initiate start-up. this bit is used to notify the transceiver of an activation request. should be set to a 1 during loopback. if xact = 1, istp is ignored; if xact = 0: 0?nitiate start-up (activation request). 1?eset state (transceiver inactive). dc 3 lpbk local loopback. 0?oopback. 1?ormal. loop back the complete 160 kbits/s u-interface bit stream at the analog output. loop- back turns off echo canceler and reconfigures the descrambler. device should be re- set and line disconnected before loopback test; istp should be set to a 1 during loopback. dc 4 afrst adaptive filter reset. 0?ormal. 1?eset. 2b+d and um set equal to 1 on do. reset halts loop transmission and clears the transceiver's adaptive filter coefficients, overriding all other transceiver control sig- nals. this provides the same functionality as the reset pin on the T7264, except f to mtc synchronization (lt) is not lost. dc 5 ldea local deactivation. 0 ?normal. 1 ?deactivate. do 2b+d and um set equal to 1. upon receiving ldea = 1 from the system device, the transceiver will save adaptive fil- ter coefficients. in the lt, the device sends three or four u superframes of dea = 0, then ceases transmission and enters the idle state. in the nt, the device deactivates upon signal loss and enters the idle state. in the nt, ldea should be set before the loss of signal (on second dea = 0) and held until xact goes low for proper deactivation. dc 6 reserved. for normal operation, this bit must be set to 1. dc 7 sksi system-to-k2. this bit may be set high or low without affecting the state of the trans- ceiver. sksi is reflected back from the T7264 across the k2 interface by means of the rsksi bit. dc 8 xpcy transparency. 0?ransparent 2b+d. 1?t mode 2b+d = 0 transmitted across the u-interface. 1?t mode 2b+d = 1 transmitted across the u-interface. this bit only affects the data transmitted on the u-interface. the u-to-k2 interface al- ways remains transparent after start-up.
20 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver k2 interface description (continued) k2 bit levels table 15. k2 data out (do) bit levels (+) active = 1 (t) transparent (? active = 0 (p) pulsing table 16. k2 device control (dc) bit levels (+) active = 1 (x) either 1 or 0 (? active = 0 bit name description true level reset/idle operational u-interface related b1, b2 isdn 64 kbits/s b1, b2 octet 1 t d isdn 16 kbits/s d bits 1 t rsf, tsf receive/transmit superframe + 1 p rf, tf receive/transmit frame + 1 p um bits eoc eoc addr, d/m, and info bits + 1 t act activate + 0 1 dea deactivate 1 1 ps1, ps2 primary/sec. power status + 1 1 febe far-end block error 1 1 ntm nt in test mode 1 1 cso cold start only + 1 0 or 1 sai s/t activity indicator + 1 1 uoa u only activation 1 1 nib network indicator bit 1 1 aib alarm indication bit 1 1 r reserved 1 1 ds bits nebe near-end bit error 1 1 xact transceiver active + 0 1 oof out of frame 0 1 bit name description true level reset/idle operational ccrc corrupt the outgoing crc x 1 istp initiate start-up 1 0 then x lpbk loopback 1 1 afrst reset + 1 then x 0 ldea local deactivate + 1 then x 0 xpcy transparency 1 0
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 21 u-interface description data is transmitted over the u-interface in 240-bit groups called u frames. each u frame consists of an 18-bit syn- chronization word (isw or sw), 12 blocks of 2b+d data (216 bits), and six overhead bits (m). a u-interface super- frame consists of eight u frames grouped together. the beginning of a u superframe is indicated by the inverted sync word (isw). the six overhead bits from each of the eight u frames, when taken together, form the 48 m bits. the following diagram shows how u frames, superframes, and m bits are mapped. 5-5171 figure 12. u-interface frame and superframe of the 48 m bits, 24 bits form the embedded operations channel (eoc) for sending messages from the lt to the nt and responses from the nt to the lt. there are two eoc messages per superframe with 12 bits per eoc message (eoc1 and eoc2). another 12 bits serve as control and status bits (ucs). the last 12 bits form the cyclic redun- dancy check (crc) which is calculated over the 2b+d data and the m4 bits of the previous superframe. figure 13 shows the different groups of bits in the superframe. 5-5172 figure 13. u-interface superframe bit groups u1 u2 u3 u4 u5 u6 u7 u8 isw[18] m[6] (2b+d) x 12 [216 bits] u-interface m bits [48] u-superframe span = 12 ms u-frame span = 1.5 ms bit # 1?8 19?34 235 236 237 238 239 240 frame # sync 12(2b+d) m1 m2 m3 m4 m5 m6 1 isw control & status (ucs) 2 3 eoc1 4 5 sw 2b+d 6 7 8 eoc2 crc
22 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver u-interface description (continued) table 17. u-interface bit assignment * lt(nt). values in parentheses () indicate meaning at the nt. k2 functional description the k2 interface provides the mechanism for transferring data and control information between the system and the T7264. a k2 frame consists of eight do octets and eight di octets which occur every 125 m s (every frame sync). figure 14 shows the k2 frame structure. 5-5173 figure 14. k2 octet description figure 15 shows the points of origination and destination of bits on the k2 and u-interfaces at the lt and nt. 5-5174 figure 15. k2 functional description bit # 1?8 19?34 235 236 237 238 239 240 frame # sync 12(2b+d) m1 m2 m3 m4 m5 m6 1 isw 2b+d eoc a1 eoc a2 eoc a3 act r 1, 5 r 1, 6 2 sw 2b+d eoc dm eoc i1 eoc i2 dea (ps 1 )* r 2, 5 febe 3 sw 2b+d eoc i3 eoc i4 eoc i5 r 3, 4 (ps 2 )* crc 1 crc 2 4 sw 2b+d eoc i6 eoc i7 eoc i8 r 4, 4 (ntm)* crc 3 crc 4 5 sw 2b+d eoc a1 eoc a2 eoc a3 r 5, 4 (cso)* crc 5 crc 6 6 sw 2b+d eoc dm eoc i1 eoc i2 r 6, 4 crc 7 crc 8 7 sw 2b+d eoc i3 eoc i4 eoc i5 uoa (sai)* crc 9 crc 10 8 sw 2b+d eoc i6 eoc i7 eoc i8 aib (nib)* crc 11 crc 12 di do b1 b2 d um1 um2 um3 dc s1 b1 b2 d um1 um2 um3 ds 1s s1 df time (125 m s) eoc ucs T7264 lt T7264 nt b1/b2/d - r(6) um1, 2 - eoc(12) um2, 3 - ps1, act, febe, ps2, ntm, cso, sai, nib df - rsf, rf, tsf, tf ds - nebe, xact, wstrt, oof um2, 3 - adea, act, rfebe, uoa, nib um1, 2 - eoc(12) b1/b2/d - r(9) dc - ccrc, afrst, istp, lpbk, xpcy, ldea df - rsf, rf, tsf, tf ds - nebe, xact, wstrt, oof dc - ccrc, afrst, istp, lpbk, xpcy, ldea b1/b2/d - r(6) um1, 2 - eoc(12) um2, 3 - ps1, act, rfebe, ps2, ntm, cso, sai, nib 2b1q 2-wire u- interface k2 k2 di do do di um2, 3 - dea, act, febe, uoa, aib um1, 2 - eoc (12) b1/b2/d - r (9)
lucent technologies inc. 23 data sheet april 1998 T7264 u-interface 2b1q transceiver k2 functional description (continued) the u superframe and the k2 superframe both occur once every 12 ms. the u frame consists of 240 bits, with eight u frames per superframe, transferred at a data rate of 160 kbits/s. the k2 superframe consists of 96 k2 frames transferred at a data rate of 512 kbits/s. in mapping the k2 to u, the blocks of 2b+d data, which occur once every k2 frame, are accumulated within the T7264 and are output in groups of twelve blocks per u frame onto the u-interface. the last 6 bits of the d octet and the s1 octet are unused on di. while every k2 frame has bits allocated for eoc messages, only two messages per u superframe are needed. k2 frame number 11 (k11) provides the data for the ?st eoc message on the u-interface, and k2 frame k59 pro- vides the data for the second eoc message. the other 94 k2 frames are unused. every k2 frame also has bits allocated for ucs data; however, only a single set of ucs data is needed in a u superframe. k2 frame num- ber k11 provides the ucs data while the other 95 k2 frames are unused. the crc is automatically generated by the T7264 and presented to the u-interface. the dc octet is used to transfer control data to the T7264 and is sampled every k2 frame. in mapping the u to k2, the 2b+d data, which occur in groups of 216 bits (12 times [2b+d]), are accumulated within the T7264 and output as one 2b+d block per k2 frame. the last 4 bits of the d octet provide indication onto the k2 interface about when data transferred on the k2 interface corresponds to data transferred on the u-interface for both transmit and receive. the eoc bits are collected by the T7264 and changed on the k2 interface twice per superframe on k2 frames k47 (held until k94) and k95 (held until k46). the ucs bits are collected by the T7264 and changed on the k2 inter- face once per superframe on k2 frame k95 (held until k94). the ds octet is used to transfer device status from the T7264 to the k2 interface. the crc is automat- ically calculated in the T7264, and a single bit (nebe) in the ds octet provides indication of a crc error. k2 framing bits the four df bits (the last 4 bits of the d octet on do) indicate when the 2b+d data from the k2 interface and u-interface correspond. a system can monitor these signals to determine when the T7264 is transmitting or receiving specific data. rsf and tsf mark the first frame (k0) of a superframe. rf and tf add resolution in identifying the start of each u frame (every twelfth k2 frame). figure 16 shows when eoc and ucs data is transferred to and from the k2 interface. it also indi- cates the occurrence of the rsf, tsf, rf, and tf bits. notice that the di and do superframes are not aligned, and therefore rsf and tsf occur at different times. 5-5175 figure 16. k2-to-u mapping rsf rf di do k0 k1 k12 k47 k59 k60 . . . . . . k95 . . . . . . k11 k48 new eoc new eoc & ucs rsf, rf rf rf rf . . . k6 k94 k0 k1 k12 k47 k59 k60 . . . . . . k95 . . . . . . k11 k48 eoc & ucs must be valid eoc must be valid . . . k6 k94 tsf tf 2 k2 frames in nt tsf, tf tf tf tf
24 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver k2 functional description (continued) figure 17 shows how the u-interface bits are grouped into eoc1, eoc2, ucs, and crc bits. it also shows how these bit groups are mapped from the u-interface to the k2 interface. 5-5176 * the u-inverted sync word (isw) is mapped to the k2 interface as the receive superframe (rsf) bit and the transmit superframe (tsf) bit. the occurrence of these bits defines the first k2 frame. figure 17. u-to-k2 mapping k2 eoc and loopback response timing each u frame contains 12 2b+d data blocks. these blocks are jitter accommodated and synchronized within the T7264 and output on the k2 interface. this introduces delay between the u-interface and the k2 interface. the re- ceive and transmit framing on the u-interface do not occur at the same time. the ansi standard specifies that the delay from u input to u output in the nt is 0.75 ms (6 k2 frames). the relationship between the k2 frame sync and the u-interface frame can change each time the device frames up. the timing delay from receive to transmit affects the eoc timing as follows: the eoc is made available on the k2 interface at do k2 frames k47 and k95, and it is sampled on di k2 frames k59 and k11. this 11-frame difference plus the two-frame delay discussed above allows a total of 13 k2 frames (1625 m s) for the system to process the eoc information and respond. thus, the system is guaranteed to have at least 1625 m s to respond to an eoc mes- sage. figure 18 shows the received and transmitted k2 frame in the nt. 5-5177 figure 18. k2 response timing m6 m5 m4 m3 m2 m1 frame # sync 1 2 3 4 5 6 7 8 isw* u - sw k - rf, tf output k0, k12, k24, . . . k84 u - eoc1 k - um1 & um2 (#1?) input k11 output k47?94 u - crc k - output ds - #1 (nebe) k - input dc - #1 (ccrc) u - 2b+d k - b1, b2, d k0, k1, . . . k95 bit # 1?8 19?34 235 236 237 238 239 240 12(2b+d) u - eoc2 k - um1 & um2 (#1?) input k59 output k95?46 u - control & status (ucs) k - um2 (#5?) & um3 input k11 output k95?94 k11 . . . k59 . . . k0 k47 . . . . . . k95 k95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . received k2 frames at nt transmitted k2 frames at nt sample eoc & ucs sample eoc new eoc new eoc & ucs . . . 2 k2 frames 1625 m s 1625 m s
lucent technologies inc. 25 data sheet april 1998 T7264 u-interface 2b1q transceiver k2 functional description (continued) k2 device status and control bits the T7264 device status bits are transmitted over the k2 interface in the ds octet. the status information includes the nebe, xact, and oof bits which are used to determine the status of the line interface and to control the activate/deactivate state machine. the T7264 device control bits are transmitted over the k2 interface in the dc octet. the control information includes the ccrc, istp, lpbk, afrst, ldea, and xpcy bits which provide the control necessary to implement the activation/deactivation state machine. tables 18 and 19 show how the dc bits are sampled and when the ds bits are available. note that a y in the column marked hyst (hysteresis) indicates that the vali- dation occurs on both entry and exit from the condition. an n in the hyst column indicates that the validation occurs only on entry into that condition. for validation, a signal must be present for three consecutive k2 frames. in lt mode, setting the ldea (local deactivation) bit causes the transceiver to send 3 or 4 superframes of dea = 0 across the u-interface, save the adaptive ?ter coef?ients, and cease transmission. in the nt mode, the ldea bit is used to ensure that the transceiver is capable of a warm start on the next acti- vation; however, the transceiver must be given advance warning prior to loss of signal. this should be done by ?tering dea = 0 for two superframe occur- rences prior to setting ldea = 1. this causes the trans- ceiver to freeze echo canceler coef?ients. the transceiver then either deactivates upon detection of loss of signal or resumes training the echo canceler if ldea = 0 is received instead of detecting loss of signal. in both lt and nt modes, the lpbk (local loopback) bit is used to request a local loopback within the trans- ceiver from the k2 input (di) to the k2 output (do). during loopback, the transceiver turns off the echo canceler (disables the canceler output from the summing node) and recon?ures the descrambler. to perform loopback, set afrst = 1 and lpbk = 1, discon- nect the u-interface metallic connection to the loop plant, then set afrst = 0 and lpbk = 0. loopback has become valid when oof = 1. in order to terminate the loopback, set afrst = 1 and lpbk = 1. reconnect the loop plant, then set afrst = 0. during the entire loop- back test, istp = 1 and xpcy may be either 0 or 1. table 18. dc octet description (control) table 19. ds octet description (status) control (dc) description hyst timing ccrc bit corrupt crc n sample k2 frames 9, 10, 11 for three consecutive ccrc = true k2 frames. continues to corrupt until the condition goes away. istp initiate start-up n sample for three consecutive k2 frames to validate. ldea local deactivate y sample for three consecutive k2 frames to validate. xpcy transparency y sample for three consecutive k2 frames to validate. afrst reset y sample for three consecutive k2 frames to validate. lpbk loopback y sample for three consecutive k2 frames to validate. status (ds) description timing nebe near-end block error presented to k2 interface on frame k95 to k94. xact transceiver active presented to k2 interface as it occurs. oof out of sync presented to k2 interface as it occurs.
26 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver k2 functional description (continued) the adea bit the adea bit is only available when the mode0 pin is set to 1 (lt mode). setting adea = 0 causes the lt to set dea = 0 on the u-interface without deactivating itself. by contrast, setting ldea = 1 at the lt causes the lt to set dea = 0 on the u-interface, save adaptive filter coefficients, and deactivate itself after sending dea = 0 for three consec- utive u superframes. in loop configurations with multiple u-interfaces, as shown in t1.601, adea is used to propagate dea = 0 beyond the local link (the link between the lt in an isdn serving switch to the next nt downstream-type element of the loop) and can be used to deactivate a nonlocal link without deactivating the local link. table 20 shows the effects of the adea and ldea bits at the lt. table 20. adea, ldea, and dea function adea at lt ldea at lt action 0 0 dea = 0 is sent downstream, but no local deactivation occurs. x 1 dea = 0 is sent downstream for 3 or 4 superframes, echo canceler coefficients are frozen, and transmission ceases. 1 0 dea = 1 is sent downstream (normal operation).
lucent technologies inc. 27 data sheet april 1998 T7264 u-interface 2b1q transceiver k2 functional description (continued) the nebe, febe, rfebe, and ccrc bits errors in the received 12-bit crc from the u-interface are indicated via the nebe (near-end block error) bit. the nebe bit is a local status bit that is set to 0 each time a crc error is detected. errors in transmitted crc can be forced by setting the ccrc (corrupt crc) bit low. because the crc error detection and corruption is handled via the nebe and ccrc bits, there is no need to have direct control or access to the 12 crc bits via the k2 interface. normally, the T7264 automatically reflects the nebe bit back to the far end as the ansi-defined febe (far-end block error) bit. the mode1 pin (pin 11) and rfebe bit can be used to alter the interaction between nebe and febe as shown in figure 19. normally, mode1 and rfebe are high, so febe is the direct result of the current state of nebe. now rfebe can be directly used to control the state of febe. the intended application for rfebe and mode1 is one having multiple u links as shown in t1.601-1992, figure e1. in this application, a performance monitoring approach called path performance monitoring can be used. this treats all links between the nt and lt as one complete link, or path. thus, any febes or nebes that occur at an intermediate element should be propagated to an endpoint. in this way, the febe and nebe counts at the endpoints represent the performance of the system as a whole. figure 20 shows how a multilink system with one inter- mediate element (ie) could use mode1, rfebe, nebe, febe, and ccrc to propagate crc errors to the endpoints. for simplicity, this figure represents only one direction of propagation of nebe and febe, namely nebes propa- gated toward the lt and febes propagated toward the nt. this circuitry would be duplicated in the opposite direction to form a complete system. at the endpoints, mode1 = 1 and rfebe = 1, so nebe and febe behave normally. at ie, mode1 = 0 so that rfebe, rather than nebe, controls the state of febe toward the far end. for clarity, the effect of mode1 is shown as a coil control for an spdt relay that selects either nebe or v cc as the upper input to the and gate. first, consider the case of a nebe occurring at the ie's lt-mode T7264. this means that a crc error occurred from nt to ie. the ie's k2 interface logic connects nebe directly to the ccrc bit of the nt-mode T7264 to force a ccrc error toward the lt. this will now show up as a nebe at the lt, effectively propagating nebe from ie to lt. now, at the lt, the nebe is reflected back toward the ie as a febe. at the ie, the k2 interface logic connects febe directly to the rfebe bit of the lt-mode T7264. this generates a febe from ie to nt, completing the path for the original crc error. thus, the result of an error from nt to ie is a nebe reported at the lt and a febe report- ed at the nt. this illustrates how the two links and the ie are treated as a single entity from a performance monitoring standpoint.
28 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver k2 functional description (continued) 5-5178a figure 19. T7264 nebe/febe/crc block diagram 5-5179a figure 20. use of rfebe in a multilink con?uration nt or lt operation the mode0 pin determines whether the device is being used in an lt system as the originator of the u-interface signals or in the nt mode as the terminator of the u-interface signal. table 21 is provided as a reference to show the different functions of the chip in nt and lt modes. table 21. mode0 pin functionality lt (mode0 = 1) nt (mode0 = 0) u-interface timing derived from mtc k2 timing derived from the u-interface transmit adea and ldea for dea, uoa, aib transmit ps1, ps2, ntm, cso, sai, nib u transmit-to-receive timing dependent upon line delay u transmit-to-receive timing fixed at 0.75 ms ldea stops transmission loss of signal stops transmission lt scrambling algorithm nt scrambling algorithm lt start-up timing nt start-up timing tl tone generation tn tone generation tn tone recognition tl tone recognition k2 interface nebe mode1 rfebe crc checker febe u-interface T7264 pin #11 2b+d+m ccrc febe nt T7264 (nt) crc generator T7264 (lt) crc checker nebe +v rfebe mode1 = 0 crc generator ccrc febe T7264 (lt) crc checker nebe +v rfebe k2 interface 2b+d+m T7264 (nt) u- inter- febe 2b+d+m mode1 = 1 rfebe = 1 lt febe intermediate element face u- inter- face logic
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 29 minimal example the simplest application of the T7264 in an nt1 is to assume only cold starts and always return an unable-to-com- ply for the eoc message. in this situation, the k2 interface signals are con?ured as shown in table 22. table 22. minimal implementation note that this is only an example and not a valid t1.601 con?uration. however, it could be useful for laboratory testing. bit name description minimal state description b1, b2 isdn 64 kbits/s b1, b2 octet t transparent d isdn 16 kbits/s d bits t transparent data in a address 000 nt address dm data or message 1 message i information 10101010 unable to comply act activation info3 transceiver active ps1, ps2 primary/sec. power status 1 always true rfebe received far-end bit error 1 not applicable ntm nt in test mode 1 never used cso cold start only 1 always cold start r reserved 1 never used data out dea deactivation 1 ignore ccrc corrupt the outgoing crc 1 never used istp initiate start-up 0 always starting lpbk loopback 1 never used afrst reset (adaptive filter reset) 0 never usedreset pin used ldea local deactivation 0 never used?lways active xpcy transparency not act received k2 act bit
30 30 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver activation and the k2 interface the signal definitions and start-up states (table 23 and figure 21) of the u-interface during activation are as re- quired by t1.601. the T7264 handles these details au- tomatically upon assertion of istp on the k2 interface or detection of a tone on the u-interface. still, for some us- ers it is useful to know what is happening at the k2 in- terface during the start-up sequence and how the system should be reacting. the following is an explana- tion of what happens during a typical start-up sequence. for simplification, it is assumed that the uoa and sai bits, defined in t1.601-1992, are held at 1 during start- up. 1. from reset to t6 at each end, xact changes from 0 to 1 to indicate that an activation request has been issued at the near end (via istp) or a wake-up tone has been detected from the far end and the transceiver is beginning the start-up se- quence. all other k2 bits are held in their reset state by the transceiver in the u-to-k2 direction at both the nt and the lt (see table 15 for these reset values). in the k2-to-u direction, the 2b+d and u overhead bits are internally overwritten by the transceivers. these bits should be initialized by the system to reflect their de- sired state at the time transparency is achieved. table 23 lists the values of the overwritten u bits at various stages of activation. 2. at t6 at the nt, oof goes high causing 2b+d transparency from the u to the k2 interface at the nt transceiver. note that the nt always frames up before the lt, due to the structure of the transceiver start-up algorithms. before t6, the nt transceiver was forcing 2b+d data on the k2 interface to all 1s. after this, the 2b+d bits on the k2 interface contain whatever is being received at the nt's u-interface on the 2b+d channels from t4 until transparency is established (see table 23 and figure 21, signal sl2). m bits in the downstream direction become transparent over the entire link. prior to this, the nt transceiver was forcing all m bits to 1 in the downstream (u-to-k2) direc- tion, except act, which was being forced to 0. in the downstream direction (k2-to-u) at the lt, m bits are al- ready being passed transparently and have been since t4. at t6, oof = 1 at the nt causes the nt to start pass- ing m bits transparently in the downstream direction. m bits in the upstream direction become transparent at the nt transceiver (k2-to-u). prior to this, the nt trans- ceiver was internally overwriting the upstream m bits to all 1s per the ansi standard (see table 23 and figure 21, signal sn2). after detecting oof = 1, the nt can set its act = 1, then wait for act = 1 from the lt. the nt is still forcing 2b+d in the upstream direction to all 1s and continues to do so until: a) it receives act = 1 from the lt b) it receives an eoc loopback message from the lt when either of the above occurs, the nt must set xpcy = 0, which enables 2b+d transparency in the up- stream direction. 3. at t7 at the lt, oof goes high causing 2b+d transparency from the u to the k2 interface at the lt transceiver. be- fore t7, the lt transceiver was forcing 2b+d data on the k2 interface to all 1s. after this, the 2b+d bits on the k2 interface contain whatever is being received at the lt's u-interface on the 2b+d channels. this is all 1s ini- tially, because the nt transceiver at the far end is forc- ing transmission of all 1s on the u-interface 2b+d channels from t1 until the transparency is established (see table 23 and figure 21, signal sn1?n3). m bits in the upstream direction become transparent over the entire link. prior to this, the lt transceiver was forcing all the m bits to 1 in the upstream (u-to-k2) di- rection, except act, which was being forced to 0. in the upstream (k2-to-u) direction at the nt, m bits are al- ready being passed transparently and have been since t6. at t7, oof = 1 at the lt causes the lt to start pass- ing m bits transparently in the u-to-k2 direction and, thus, affects full m-bit transparency in the upstream di- rection. since the lt is receiving m4 bits from the nt, it can de- tect when the nt has changed its act bit from 0 to 1. af- ter getting act = 1 three consecutive times from the nt, the lt may set its xpcy = 0 and act = 1, resulting in 2b+d transparency in the downstream direction over the entire link. prior to this, the lt transceiver was inter- nally overwriting the downstream 2b+d data to all 0s per t1.601.
lucent technologies inc. 31 data sheet april 1998 T7264 u-interface 2b1q transceiver activation and the k2 interface (continued) there is one case in which the lt never receives act = 1 from the nt. if the lt is connected to an nt1, which has no te controlling it, the nt can never send act = 1. t1.601 (section 6.4.6.6) states that transparency required to perform loopbacks must be provided when loopbacks are requested, even when the nt is not sending act = 1. in this case, the lt, once it has received oof = 1, must transmit the proper eoc message to enable the desired remote loopback. the nt1 must set its xpcy = 0 in response to the eoc loopback message. upon receiving the echoed message from the nt, the lt must set xpcy = 0. now, transparency is established over the entire link without having set the act bits to 1. upon receiving act = 1 three consecutive times from the lt, or upon receiving an eoc loopback message as discussed above, the nt sets its xpcy = 0, affecting 2b+d transparency in the upstream direction over the entire link. prior to this, the nt transceiver was inter- nally overwriting the upstream 2b+d data to all 1s per t1.601. the link is now fully operational. table 23. de?itions of signals during start-up * tones have alternating pattern of four +3s, followed by four ?s, and no sw. ? see figure 21 for start and/or stop time of this signal. signals sn3 and sl3 continue indefinitely (or until deactivation). notes: tn, tl tones produced by nt or lt, respectively. snx, slx pulse patterns produced by nt or lt, respectively. tx notation refers to transition instants defined in figure 21. absent under superframe, this notation means that only sw is transmitted, not isw. normal normal means that the m bits are transmitted onto the 2-wire line as required during normal operation (e.g., valid crc bits, eoc bits, and indicator bits are transmitted). normal + except to perform a loopback, 2b+d bits remain in the previous state (sn2 or sl2) until both act bits indicate full transparency of the b- and d-channels (i.e., the 2b+d bits of sn3 and sl3 must remain set to 1 and 0, respectively, until transparency is achieved at both ends of the dsl). priority priorities exist for responding to several signals as follows: 1. reset 2. afrst 3. iloss 4. tone detection 5. istp 6. lpbk signal sync word (sw) superframe (isw) 2b+d m start stop time (frames) tn 3* 3* 3* 3* ? ? 6 sn1 present absent 1 1 t1 t2 sn2 present absent 1 1 t5 t6 sn3 present present normal + normal t6 tl 3* 3* 3* 3* ? ? 2 sl1 present absent 1 1 t3 t4 sl2 present present 0 normal t4 t7 sl3 present present normal ? normal t7
32 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver activation and the k2 interface (continued) 5-5180 notes: t0 reset state. t1 network and nt are awake. t2 nt discontinues transmission, indicating that the nt is ready to receive signal. t3 network responds to termination of signal and begins transmitting signal toward the nt. t4 network begins transmitting sl2 toward the nt, indicating that the network is ready to receive sn2. t5 nt begins transmitting sn2 toward the network, indicating that nt has acquired sw frame and detected sl2. t6 nt has acquired superframe marker, and is fully operational. t7 network has acquired superframe marker, and is fully operational. figure 21. state sequence for dsl transceiver start-up applications the T7264 is intended for use in both switch and customer premises equipment including a central office (co), a private branch exchange (pbx), a 2-wire to 4-wire converter (nt1), and terminal equipment (te). the physical ter- mination of the u-interface at the network end is referred to as the line termination (lt); the physical termination at the user end is referred to as the network termination (nt). figure 22 shows a loop configuration using several u- interface devices at various locations. the T7264 provides system access to the u loop through the k2 interface. the k2 interface is a tdm serial interface which provides access to 2b+d data, u-interface maintenance, and T7264 device control/status. figure 23 shows a 2-wire terminal application with the T7264 providing the u-interface. the t7270 provides the microprocessor with access to the individual octets of the k2 data stream. the b1 and b2 data could be transferred to either a codec for voice communications, such as the t7513a, or to an hdlc controller for data communications, such as the t7121. another t7121 could provide microprocessor access to d-channel hdlc processing. the microprocessor would control initialization, activation/deactivation, d-channel processing, and maintenance func- tions. ab c d a + c 5 s for cold start a + c 150 ms for warm start b + d 10 s for cold start b + d 150 ms for warm start 4 ms 480 ms t0 t1 t5 tn sn1 (op- tional) 6 frames nt network nt network sl1 (optional) sl2 sl3 sn2 sn3 tl 2 frames t2 t3 t6 t7 t4
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 33 applications (continued) figure 24 shows a digital pair gain application with the T7264 providing the u-interface. in this system, the u-inter- face is used as a digital pipe to multiplex two analog voice lines onto the b channels. thus, one twisted pair can provide two analog lines. the t7270 forms the interface between the microprocessor, the k2 bus, and the codecs. the t7121 can be used for hdlc formatting on the b or d channels to provide enhanced features. the divider pro- vides the 2.048 mhz clock for the codecs, which are interfaced to the tsi via its chi ports. the codecs and battery feeds provide the analog interface to the telephones. 5-5181 figure 22. loop application 5-5182 figure 23. 2-wire terminal application 5-5183 figure 24. digital pair gain application 2-wire 2b1q u-interface 2-wire 2b1q u-interface u nt u lt u lt switch pbx or nt1 4-wire s/t u nt 2-wire 2b1q u-interface micro- processor t7270 k2 t7121 hdlc t7513b codec t7121 hdlc handset db1b2 data T7264 chi transformer/ protection u-interface 2754h/ 521a 2b1q T7264 tsi t7270 hifi-64 t7121 10.24 mhz k2 interface codec codec t7513b battery feed analog interface battery feed lb1276af 4th chi microprocessor rs232c for maintenance monitor terminal async data port divider 2.048 mhz chi
34 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to de?e the model. no industry-wide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison. the hbm esd threshold presented here was obtained by using these cir- cuit parameters: recommended operating conditions * to meet ansi t1.601 free-run line rate requirement, nt tolerance is 100 ppm. ? x = tolerance of mtc. parameter min typ max unit storage temperature ?5 125 c lead temp (soldering or bonding) 300 c any pin to gnd ?.5 6.5 v power dissipation (package limit) 700 mw esd threshold voltage device voltage T7264-ml >500 parameter symbol test conditions min typ max unit ambient temp t a v dd = 5 v 5% ?0 85 c any v dd v dd 4.75 5.0 5.25 v gnd to gnd v gg ?0 10 mv voltage ref capacitor cvr 0.08 0.1 0.2 m f master clock frequency mclk 15.36 mhz master clock tolerance mclk nt mode lt mode ?25* ?25 + x* ? 225* 225 ?x* ? ppm ppm master clock duty cycle mclk 47 ? 53 %
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 35 electrical characteristics all characteristics are for a 15.36 mhz crystal, 135 w line load, random 2b+d data, v dd = 5 v 0.25 v, ?0 c to +85 c, output capacitance = 50 pf. table 24. power consumption table 25. performance ratings table 26. crystal characteristics: fundamental mode crystal these are the characteristics of a crystal for meeting the 100 ppm requirements of t1.601 for nt operation. the parasitic capacitance of the pc board to which the T7264 crystal is mounted must be kept within the range 0.6 0.4 pf. for lt operation or for nt applications that can tolerate a free-running frequency tolerance of up to 150 ppm, t ol and c m may be relaxed as long as they satisfy the following: | t ol + (3300 ppm) x c m (in pf) | 150 ppm using the nominal value of c m . all other parameters are unchanged except that the shunt capacitance, c o , should change in proportion with any change in c m . possible sources for 15.36 mhz crystals for use with the T7264 include: * mtron is a registered trademark of mtron industries, inc., a wholly owned subsidiary of lynch corporation. (lynch is a registered trade- mark of lynch corporation.) parameter test conditions min typ max unit power consumption operating, random data 275 350 mw power consumption powerdown mode 30 50 mw parameter test conditions min typ max unit warm start time 200 ms cold start time 3.5 s error rate over 18 kft 26 awg cable 10 ? parameter symbol test conditions specifications unit center frequency f o with 25.0 pf of loading 15.36011 mhz tolerance including calibration, temperature stability, and aging t ol 60 ppm drive level d l maximum 0.5 mw series resistance r s maximum 20 w shunt capacitance c o 3.0 20% pf motional capacitance cm 12 20% ff cts knights mtron* saronix tom haney at 1-704-684-0242 p/n 020-2807-0 william j. winch (winch sales associates) at 1-908-613-1515 p/n 4044-001 laura derrickson at 1-800-227-8974 (in ca, 1-800-422-3355 p/n srx5144(-n) for lt applications, a relaxed speci?ation part is avail- able where tol = 85 ppm and cm = 18 ff 20%. p/n srx5152(? [no vinyl coating])
36 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver electrical characteristics (continued) table 27. internal pll characteristics * set by digital pll; therefore, variations track mtc (lt mode) or u-interface line rate (nt mode). table 28. digital dc characteristics (over operating ranges) loop-range performance characteristics the T7264 transceiver is designed to allow systems to meet the loop-range requirements of ansi standard t1.601- 1992 when the transceiver is used with the proper peripheral circuitry. the line driver provides pulses that produce the 2.5 v template required of the t1.601 specification when connected to the proper transformer and interface circuitry. parameter test conditions min typ max unit total pull range 250 ppm jitter transfer function ? db point (lt) ? db point (nt), 18 kft 26 awg 0.45* 5* hz hz jitter peaking at 0.15 hz typical (lt) at 1.5 hz typical (nt) 0.4* 1.0* db db parameter symbol test conditions min typ max unit input leakage current: low high low high i il i ih i ilpu i ihpu v il = 0 (pin 1, 2) v ih = v dd (pin 1, 2) v il = 0 (pins 7?1, 14?5, 24?6) v ih = v dd (pins 7?1, 14?5, 24?6) ?0 ?2 10 ?0 10 m a m a m a m a input voltage: low high low-to-high threshold high-to-low threshold low high v il v ih v ils v ihs v ilc v ihc all pins except pin 7, 10, 11, 24 all pins except pin 7, 10, 11, 24 pin 7 pin 7 pins 10, 11, 24 pins 10, 11, 24 2.0 v dd ?0.5 0.7 v dd 0.8 0.5 0.2 v dd v v v v v v output leakage: low high i ozl i ozh v ol = 0; pin 26 = 0 v oh = v dd; pin 26 = 0 10 ?0 m a m a output leakage: low, ttl high, ttl v ol v oh i ol = 1.6 ma, pins 3, 4, 5, 16 i ol = 3.3 ma, pin 43 i ol = 6.5 ma, pins 13, 23 i oh = 2.4 ma, pins 3, 4, 5, 16 i oh = 5.1 ma, pin 43 i oh = 10.4 ma, pins 13, 23 2.4 2.4 2.4 0.4 0.4 0.4 v v v v v v
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 37 timing characteristics output capacitance = 50 pf, t a = ?0 c to +85 c, v dd = 5 v 5%, gnd = 0 v, crystal frequency = 15.36 mhz. table 29. clock timing (see figures 25, 26, and 28.) * includes the effect of phase steps generated by the digital phase-locked loop. 5-5184 figure 25. timing diagram referenced to f 5-5185 figure 26. timing diagram referenced to c symbol parameter min typ max unit f 8 khz duty cycle 49.8 50.2 % c 512 khz duty cycle 46 54 % rclken 80 khz duty cycle 48 52 % ckout duty cycle: in 7.68 mhz mode in 15.36 mhz mode pulse width (high) in 10.24 mhz mode 45 40 23* 55 60 52* % % % tr1, tf1 rise or fall time 30 ns tchfh, tfhch clock (c) high to frame sync (f) ?5 15 ns trchrch ckout clock to rclken clock enable 25 ns tcolfh ckout clock to frame sync (f) 50 ns tdivcl, tcldiz receive data (di) setup & hold time 50 ns tchdov clock (c) high to data (do) valid 50 ns tr2, tf2 ckout clock rise or fall 15 ns tchosv clock (c) high to out of sync osync valid 60 ns f ckout tcolfh c tfhch tf1 tf1 tr1 tf2 tr2 rclken tf1 tr1 trchrch tchfh c do tchdov di tdivcl tcldiz osync tchosv tdivcl tcldiz f bit 1 bit 1 of b1 data bit 2 bit 2 of b1 data
38 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver timing characteristics (continued) table 30. mtc requirements and characteristics* (lt mode) * to meet ansi t1.601-1992, see note for recommended operating conditions. ? one ui = 12.5 m s. table 31. reset timing (see figures 27 and 28.) 5-5186 figure 27. reset timing diagram switching test input/output waveform 5-5187 figure 28. switching test waveform parameter min typ max unit mtc clock period 125 ?32 ppm 125 125 + 32 ppm m s mtc high/low time 8 mclks mtc rise/fall time 60 ns mtc jitter 0.259 ui ? symbol parameter min max unit trslfl, tflrsh reset setup and hold time 60 ns trslrsh reset low time: from idle mode or normal operation from power on 3 1.5 k2 frames ms f reset (rs) trslfl tflrsh trslrsh 2.0 v 0.8 v test points 2.4 v 0.4 v 2.0 v 0.8 v 2.4 v 0.4 v
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 39 outline diagram dimensions are in millimeters. 5-2506 notes: meets all jedec standards. pin 1 index mark may be a dimple or numeric located in zones indicated. ordering information code package temperature comcode T7264a- -ml-d 44-pin plcc ?0 c to +85 c 107890170 T7264a- -ml-dt 44-pin plcc ?0 c to +85 c 107997124 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max
40 40 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers introduction the questions and answers are divided into three cate- gories: u-interface, k2 interface, and miscellaneous. for detailed application information, also refer to the application notes implementation of an ansi standard isdn nt1 using the lucent t7262a/63, t7252a, t7270, and an 8-bit microcontroller and performance factors in line-powered 2b1q applications. u-interface q1 : is the line interface for the T7264 the same as the t7262a/63? a1 : the interface is different in that the t7262a/63 uses a lucent 2754g transformer (2.5:1 turns ratio), and the T7264 uses a lucent 2754h trans- former (1.5:1 turns ratio). other changes to the line interface include device-side resistors of 16.9 w 1% and line-side resistors of 16.9 w 7%. part of the line-side resistance will likely be a ptc in those applica- tions requiring power cross protection. the T7264 device-side protection is unchanged (521a diodes), and the dc blocking capacitor is unchanged (illinois capacitor* 1.0 m f 5%). line-side protection must be tailored to individual system needs. q2 : why is a higher transformer magnetizing inductance used (as compared to other vendors)? a2 : it has been determined that a higher inductance provides better linearity. furthermore, it has been found that a higher inductance at the far end pro- vides better receiver performance at the near end and better probability of start-up at long loop lengths. q3 : can the T7264 be used with a transformer that has a magnetizing inductance of 20 mh? a3 : the echo canceler and tail canceler are optimized for a transformer inductance of approx- imately 80 mh and will not work with a value this low. q4 : are the lucent u-interface transformers available as surface-mount components? a4 : not at this time. q5 : are there any future plans to make a smaller height 2-wire transformer? a5 : due to the rigid design speci?ations for the transformer, vendors have found it dif?ult to make the transformer any smaller. we are con- tinuing to work with transformer vendors to see if we can come up with a smaller solution. q6 : the line interface components speci?ations require 16.9 w resistors on the line side of the transformer. we would like to change this value for our application. can the u-interface line-side circuit be redesigned to change the value of the line-side resistors? a6 : yes. for example, the line-side resistances can be re?cted back to the device side of the trans- former so that, instead of having 16.9 w on each side of the transformer, there are no resistors on the line side of the transformer and 24.4 w resis- tors on the device side (16.9 + 16.9/n 2 , where n is the turns ratio of the transformer). however, there may be some performance penalty in this case since the on-chip hybrid network is opti- mized for 16.9 w of resistance on the device side of the transformer. * illinois capacitor is a registered trademark of illinois capacitor inc.
lucent technologies inc. 41 data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) q7 : why are the line-side resistors (16.9 w ) rated at 7% tolerance in figure 4 of the data sheet? a7 : this tolerance was determined based on analysis of the output voltage tolerance of the t7262a/63 solution as compared to the T7264 solution, taking into account the tolerances of the transformer, resistors, etc. it is not a standard resistor tolerance, such as 5%, because as much ?xibility as possible was desired. the 16.9 w resistor is often a combination of a resistor and a positive temperature coef?ient (ptc) surge- protection resistor, and ptcs generally have wider tolerances. some 2b1q manufacturers try to match the ptcs in such a way that their variations from the nominal value are in the same direction. how- ever, it is important to use as tight a tolerance as possible for the following reasons: n the 16.9 w resistor is also part of the termina- tion impedance looking into tip/ring. ansi speci?s this impedance at 135 w nominal, and the impedance template over the speci?d frequencies is derived from the return loss requirement (t1.601, sections 7.1, 7.2, and figure 19). a tighter tolerance on the 16.9 w resistors allows more margin on the return loss template. n if resistors are unmatched, longitudinal balance (described in t1.601, section 7.3) may be affected. designers can experimentally deter- mine the maximum tolerance allowed in their system by varying the 16.9 w resistors slightly and observing the effect on the parameters mentioned above. q8 : the dc blocking capacitor speci?d is 1 m f. can it be increased to at least 2 m f? a8 : yes. this value can be increased without any det- rimental effect. q9 : the application diagram in the data sheet shows the loopback relay on the line side of the trans- former. why is it not shown on the device side? a9 : the relay can be located on the device side between the 521a surge protector and the trans- former, and the local loopback will function prop- erly. it is shown on the line side because in many applications the relay is a dpdt type and is also used for metallic access to some line testing equipment (at an lt, for example). q10 : if the relay is on the line side, what type should it be? a10 : relay type is application-dependent. an example of a relay which would work in most cases is an aromat* ds series 2 a relay. q11 : clarify the meaning of the note concerning the 3000 pf capacitors in the u-line interface ?ure (figure 4). a11 : the capacitors are not absolutely required. the ansi t1.601 speci?ation contains no require- ments on longitudinal noise immunity. therefore, these capacitors are not required in order to meet the speci?ation. however, there are guidelines in iec 801-6 which suggest a noise immunity of up to 10 vrms between 150 khz and 250 mhz. at these levels, the 10 khz tone detector in the T7264 may be desensitized such that tone detec- tion is not guaranteed on long loops. the 3000 pf was selected to provide attenuation of this common-mode noise so that tone detector sensitivity is not adversely affected. since the 3000 pf capacitor was selected based only on guidelines, it is not mandatory, but it is recom- mended in applications which may be susceptible to high levels of common-mode noise. the ?al decision depends on the speci? application. * aromat is a registered trademark of aromat corporation.
42 42 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) q12 : why must secondary protection, such as the 521a protection diode, be used? a12 : the purpose of the 521a is to protect against metallic surges below the breakdown level of the primary protector. such metallic surges will be coupled through the transformer and could cause device damage if the currents are high. the 521a does not provide absolute protection for the device, but rather works in conjunction with the built-in protection on the device leads. the breakdown voltage level for secondary pro- tection devices must be chosen to be above the normal working voltage of the signal and typically below the breakdown voltage level of the next stage of protection. the 521a has a minimum breakdown voltage level of 6.95 v and a maxi- mum breakdown voltage of 8.0 v. the chip pins which the 521a protects are pins 36 (hp), 31 (hn), 32 (lop), and 35 (lon). the 16.9 w resistors will help to protect pins 32 and 35, but pins 31 and 36 will be directly exposed to the voltage across the 521a. the on- chip protection on these pins consists of output diodes and a pair of polysilicon resistors. these pins have been thoroughly tested to ensure that an 8 v level will not damage them; therefore, no third level of protection is needed between the 521a and the hp and hn pins. the 521a has a maximum reverse surge voltage level of 10 v at 50 a. sustained currents this large are not a concern in this application, since it is assumed that some form of primary protection is being used, such as the teccor* p2103aa sidactor *. thus, there should never be more than 8.0 v across the 521a, except for possibly an esd or lightning hit. in these cases, the T7264 is able to withstand at least 500 v (human-body model) on its pins. another consideration is the capacitive loading that the protection device presents to the target device. this is generally required to be negligible at the operating frequency. from a practical point of view, the device is chosen to meet not only voltage, current, and capacitance requirements, but also to meet price, availability, manufacturing, and second- sourcing requirements. the 521a device is a general-purpose device that meets system requirements for voltage, current, capacitance, price, etc., for some of lucents customers. other devices which may be acceptable alternates are as follows: motorola ? sa6.0c (through-hole and surface-mount), microsemi smsj6.0c-smb (sur- face-mount), and sgs-thomson sm6t6v8c (surface-mount). q13 : bellcore tr-tsy-000078, section 3.2.4.1, prohib- its using silver metallization, but the 521a protec- tion diodes have silver-plated leads. does this indicate an incompatibility problem? a13 : bellcore tr-tsy-000078, section 3.2.4.1 prohib- its silver ? . . when electromigration is a problem. the 521a diodes are only used as secondary protection, and, therefore, almost never carry any current. electromigration occurs only when there is a high current ?w for an extended period of time. since the diodes are never subjected to this condition, electromigration is not a problem, and the silver plating is acceptable. q14 : where can information be obtained on lightning and surge protection requirements for 2b1q products? a14 : ansi t1.601, appendix b, provides a list of applicable speci?ations to which you may refer. also, there are many manufacturers of overvolt- age protection devices who are familiar with the speci?ations and would be willing to assist in surge protection design. the itu-t k series recommendations are also a good source of information on protection, especially recommen- dation k.11, ?rinciples of protection against overvoltages and overcurrents, which presents an overview of protection principles. * teccor and sidactor are trademarks of teccor, inc. ? motorola is a registered trademark of motorola, inc. ?sgs-thomson is a registered trademark of sgs-thomson microelectronics, inc.
lucent technologies inc. 43 data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) q15 : itu-t speci?ation k.21 describes a lightning surge test for nt1s (see figure 1/k.21 and table 1/k.21, test #1) in which both tip and ring are connected to the source and a 1.5 kv voltage surge is applied between this point and the gnd of the nt1. what are the protection consid- erations for this test? are the hp and hn pins susceptible to damage? a15 : the critical component in this test is the trans- former since its breakdown voltage must be greater than 1.5 kv. assuming this is the case, the only voltage that will make it through to the secondary side of the transformer will be prima- rily due to the interwinding capacitance of the transformer coils. this capacitance will look like an impedance to the common-mode surge and will therefore limit current on the device side of the transformer. the device-side voltage will be clamped by the 521a device. the maximum breakdown voltage of the 521a is 8 v. the 16.9 w resistors will help protect the lop and lon pins on the T7264 from this voltage. however, this voltage will be seen directly on pins 36 and 31 (hp and hn) on the T7264. the on-chip protection on these pins con- sists of output diodes and a pair of polysilicon resistors. these pins have been thoroughly tested to ensure that an 8 v level will not damage them; therefore, no third level of protection is needed between the 521a and the hp and hn pins. q16 : how is it possible to guarantee the 0.35 db power spectrum tolerance on the u-interface? a16 : by trimming to 0.1 db; the rest of the variation is for power supply, temperature, and aging. q17 : is the 100 ppm free-run frequency (nt mode) recommendation met in the T7264? a17 : in the free-run mode, the output frequency is primarily dependent upon the crystal, not the sili- con design. for low-cost crystals, initial toler- ance, temperature, and aging effects may account for two-thirds of this budget, and just a couple of pf of variation in load capacitance will use up the rest. thus, the 100 ppm goal can be met if the crystal parameters are well controlled. see the crystal characteristics information in the data sheet (table 26). q18 : it has been noted in some other designs that the crystal has a capacitor from each pin to ground. changing these capacitances allows the fre- quency to be adjusted to compensate for board parasitics. can this be done with the T7264 crys- tal? also, can we use a crystal from our own manufacturer? a18 : the crystal for the T7264 is tuned to a particular load capacitance that does not include external capacitors. the advantage to this is that no exter- nal components are required. the disadvantage is that board parasitics must be very small. the data sheet notes that the board parasitics must be within the range of 0.6 pf 0.4 pf. lucent does not require that a particular crystal be used, but we strongly recommend adhering to the crys- tal parameters speci?d in the data sheet. a crystal which deviates from these parameters can work under most conditions, but we cannot guarantee that it will start up and/or meet the 100 ppm requirement under all operating condi- tions. q19 : is there a test pin available for generating a +3/? sequence so that pulse templates can be measured easily? a19 : there is no such pin. but a sequence of four +3s, followed by four ?s (and so on) is the 10 khz wakeup tone (tn, tl in ansi t1.601, figure 17) that each transceiver outputs when initiating a start-up. this tone is produced when the k2 bit, istp in the dc octet, is asserted. at the nt, this tone lasts for 9 ms (90 pulses), and at the lt, it lasts for 3 ms (30 pulses). this should be long enough to capture the data on a digitizer or stor- age scope for analysis. q20 : what are the average cold start and warm start times? a20 : lab measurements have shown the average cold start time to be about 3.3 s?.2 s over all loop lengths, and the average warm start time to be around 125 ms?90 ms over all loop lengths. q21 : what is the u-interfaces response time to an incoming wakeup tone from the lt? a21 : response time is about 1 ms. q22 : what is the minimum time for a u-interface reframe after a momentary (<480 ms) loss of synchronization? a22 : five superframes (60 ms).
44 44 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) q23 : can the range of the T7264 on the u-interface be speci?d in terms of loss? what is the range for over straight 24 awg wire? a23 : ansi standard t1.601, section 5.1, states that transceivers meeting the u-interface standard are intended to operate over cables up to the limits of 18 kft (5.5 km) 1300 w resistance design. resis- tance design rules specify that a loop (of single- or mixed-gauge cable; e.g., 22 awg, 24 awg, and 26 awg) should have a maximum dc resis- tance of 1300 w , a maximum working length of 18 kft, and a maximum total bridged tap length of 6 kft. the standard states that, in terms of loss, this is equivalent to a maximum insertion loss of 42 db @ 40 khz. lucent has found that, for assessing the condition of actual loops in the ?ld in a 2b1q system, specifying insertion loss as 33.4 db @ 20 khz more closely models ansi circuit operation. this is equivalent to a straight 26 awg cable with 1300 w dc resistance (~15.6 kft). the above goals are for actual loops in the out- side loop plant. these loops may be subjected to noise and jitter. in addition, as mentioned above, there may be bridge taps at various points on the loop. the t1.601 standard de?es 15 loops, plus the null, or 0 length loop, which are intended to represent a generic cross section of the actual loop plant. a 2b1q system must perform over all these loops in the presence of impairments with an error rate of <1e?. loop #1 (18 kft, where 16.5 kft is 26 awg cable and 1.5 kft is 24 awg cable) is the longest, and so has the most loss (37.6 db @ 20 khz and 47.5 db @ 40 khz). note that this is more loss than discussed in the preceding para- graph. the difference is based on test require- ments vs. ?ld deployment. the test requirements are somewhat more stringent than the ?ld goal in order to provide some margin against severe impairments, complex bridged taps, etc. if a transceiver can operate over loop #1 error- free, it should have adequate range to meet all the other loops speci?d in t1.601. loop #1 has no bridged taps, so passing loop #1 does not guarantee that a transceiver will successfully start up on every loop. also, due to the complex nature of 2b1q transceiver start-up algorithms, there may be shorter loops which could cause start-up problems if the transceiver algorithm is not robust. the T7264 has been tested on all of the ansi loops per the t1.601 standard and passes them all successfully. two loops com- monly used in the lab to evaluate the perfor- mance of the T7264 silicon are as follows: the T7264 is able to start up and operate error- free on both of these loops. neither of these loops is speci?d in the ansi standard, but both are useful for evaluation purposes. the ?st loop is used because it is simple to construct and easy to emulate using a lumped parameter cable model, and it is very similar to ansi loop #1, but slightly worse. thus, if a transceiver can start up on this loop and operate error-free, its range will be adequate to meet the longest ansi loop. the second loop is used because, due to its dif? cult bridge tap structure and its length, it stresses the transceiver start-up algorithms more than any of the ansi-de?ed loops. thus, if a transceiver can start up on this loop, it should be able to meet any of the ansi-de?ed loops which have bridge taps. also, on a straight 26 awg loop, the T7264 can successfully start up at lengths up to 21 kft. this fact, combined with reliable start-up on the 15 kft 2bt loop above, illustrates that the T7264 provides ample start-up sensitivity, loop range, and robustness on all ansi loops. another parameter of interest is pulse height loss (phl). phl can be de?ed as the loss in db of the peak of a 2b1q pulse relative to a 0 length loop. for an 18 kft 26 awg loop, the phl is about 36 db, which is 2 db worse than on ansi loop #1. a signal-to-noise ratio (snr) measure- ment can be performed on the received signal after all the signal processing is complete (i.e., at the input to the slicer in the decision feedback equalizer). this is a measure of the ratio of the recovered 2b1q pulse height vs. the noise remaining on the signal. the snr must be greater than 22 db in order to operate with a bit error rate of <1e?. loop con?- uration bridge taps (bt) loss @ 20 khz (db) loss @ 40 khz (db) 18 kft 26 awg none 38.7 49.5 15 kft 26 awg 2 at near end, each 3 kft, 22 awg 37.1 46.5
lucent technologies inc. 45 data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) a23: (continued) with no impairments, the T7264 snr is typically 32 db on the 18 kft 26 awg loop. when all ansi- speci?d impairments are added, the snr is about 22.7 db, still leaving adequate margin to guarantee error-free operation over all ansi loops. finally, to estimate range over straight 24 awg cable, the 18 kft loop loss can be used as a limit (since the T7264 can operate successfully with that amount of loss), and the following calcula- tions can be made: = 24 kft therefore, the operating range over 24 awg cable is expected to be about 24 kft. q24 : what cable simulator is used for evaluating the T7264? a24 : the original version of the transceiver was tested using real cable for ansi loop performance mea- surements. however, currently, the lucent tech- nologies microelectronics group laboratory uses the tas2200a* cable emulator for evaluation purposes. q25 : the data sheet states that the T7264 meets the ansi t1.601-1992 standard. is there detailed evaluation data available on loops 1 and 4? a25 : the results shown in the following table for some typical devices have been obtained in laboratory testing. loops 1 and 4 are the most dif?ult cases. q26 : what does the energy spectrum of a 2b1q signal look like? a26 : figure a1 (curve p1) in the ansi t1.601 standard gives a good idea of what this spectrum looks like. q27 : does the return loss measurement described in ansi t1.601, section 7, require that the T7264 terminate a metallic cable with 135 w during powerdown? a27 : no. ansi and etsi speci?ations do not require this. they require that the device be placed in an active mode with the transmitter producing 0 v (same as quiet mode) while performing the return loss measurements. the T7264 is placed in this mode by pulling the reset pin low. q28 : how is the T7264 set to quiet mode? a28 : the device is placed in the quiet mode by pulling the reset pin low. in this mode, the transmitter is on, but is producing 0 v. q29 : please clarify the meaning of ansi standard t1.601, section 7.4.2, jitter requirement #3. a29 : the intent of this requirement is to ensure that after a deactivation and subsequent activation attempt (warm start), the phase of the receive and transmit signals at the nt will be within the speci?d limits relative to what they were prior to deactivation. this is needed so that the lt, upon a warm-start attempt, can make an accurate assumption about the phase of the incoming nt signal with respect to its transmit signal. note that the T7264 meets this requirement by design because the nt phase offset from transmit to receive is always ?ed. q30 : how can proprietary messages be passed across the u-interface? a30 : the embedded operations channel (eoc) provides one way of doing this. ansi de?es 64 8-bit messages which can be used for non- standard applications. they range in value from binary 00010000 to 01000000. there is also a provision for sending bulk data over the eoc. setting the data/message indicator bit to 0 indicates the current 8-bit eoc word con- tains data that is to be passed transparently with- out being acted on. note that there is no response time requirement placed on the nt in this case (i.e., the nt does not have to echo the message back to the lt). also note that as of 1993 this is only an ansi provision and is not an ansi requirement. the T7264 does support this provision. * tas2200a is a trademark of telecom analysis systems incorpo- rated. loss of 18 kft 26 awg loop @ 20 khz 38.7 db loss per kft of 24 awg cable @ 20 khz 1.6 db ansi loop # con?uration 1992 ansi xtalk margin (db) 1 lt 1.9 4 lt 7.6 38.7 db 1.6 db/kft ---------------------------
46 46 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) k2 interface q31 : how are powerdown and warm start performed in the T7264? a31 : the powerdown/warmstart sequence is as fol- lows: n at the lt, the series of events begins with the assertion of ldea = 1. this causes the device to begin the automatic deactivation sequence. as long as the device control bits (istp, lpbk, and afrst) and the r ese t and iloss pins remain inactive during this time, the lt device con- cludes deactivation by entering the powerdown state. from this condition, the loop can be reactivated by using a warm start. n at the nt, the device receives at least three consecutive ldea = 0 bits from the lt during deactivation. these bits must be read from the k2 interface and interpreted to indicate that a deactivation is occurring. once this condition is detected, the external controller must set ldea = 1 at the nt, causing the device to freeze its signal processor coef?ients and power down when a loss of signal from the lt is detected. during this time, the device control bits (istp, ipbk, afrst, etc.) and the reset and ilos s pins must remain inactive at the nt. from this condition, the loop can be reactivated with a warm start. q32 : does the device automatically reset and attempt a cold start if out of frame (oof) occurs after a warm start? a32 : when an oof condition occurs, the device enters a reframing algorithm and attempts to regain syn- chronization. during this time, the device is still active. if, after 480 ms, the device has not regained synchronization, it goes into the deac- tive state, from which the next start-up attempt will result in a cold start. this conforms to the state tables shown in appendix c of ansi t1.601. q33 : what is the purpose of the sksi bit in the device control (dc) octet? a33 : its primary use is to detect a ?tuck at one condi- tion on the k2 interface. it is re?cted back onto the k2 interface as rsksi in the ds octet. setting sksi to 0 will guarantee that at least one bit (rsksi) will be zero on the received k2 interface. q34 : what should the state of the other bits in the dc octet be during a local u-loopback? a34 : to perform a loopback, the following sequence of bits are set in the dc octet, where 1 resets the device and puts it into a known state, 2 asserts the loopback, and 3 resets the chip again and removes the loopback. the other dc bits should be kept in their inactive state: q35 : what is the state of the do bits when osync goes low momentarily after the link is up? a35 : the 2b+d data and u-overhead bits are passed transparently from the u-interface to the k2 interface. since this u-information is likely to be invalid during this time, the system should recog- nize this and disregard the data and overhead bits during this time. note that this situation is dif- ferent than when osync is low prior to a start- up. in the latter case, the 2b+d and overhead bits are internally overwritten by the transceiver to default values until synchronization is achieved (see the data sheet for these values). in either case, the ds bits are always valid. q36 : ansi requires 0.75 ms to process the eoc mes- sage at the nt before echoing it. the T7264 data sheet, however, states that the time from when an incoming message becomes available and the next message goes out is 1.75 ms. how can the T7264 meet the standard? a36 : the 0.75 ms in the ansi requirement refers to the delay between the start of the received u frame and the start of the transmitted u frame. in the eoc bit locations, there are sw/isw plus 12 2b+d blocks of data between the last bit of one eoc message and the ?st bit of the next one. this provides an additional 1.46 ms of processing time or a total of 2.21 ms. of course, some of this time is consumed by the T7264 in moving data between the u and k2 interfaces. after these delays are taken into consideration, 1.75 ms remain to process data. 1. afrst = 1, ipbk = x, istp = 1, xpcy = x [loopback = inactive] 2. afrst = 0, ipbk = 0, istp = 1, xpcy = x [loopback = active] 3. afrst = 1, ipbk = 1, istp = 1, xpcy = x [loopback = inactive]
lucent technologies inc. 47 data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) q37 : what are the requirements on the transmission and reception of eoc data on the k2 interface? a37 : this is described on page 24, figure 18, of this data sheet. to summarize, the received eoc data changes at k2 frames 47 and 95 (where frame 0 is marked by the rising edge of rsf). the most recent eoc data is continuously available on the k2 bus in the intervals between frames 47 and 95. the eoc data to be transmitted must be present on the k2 interface at outgoing k2 frames 11 and 59 (where frame 0 is marked by the rising edge of tsf). since it is sampled only at those times, it does not matter what is present in those bit positions in the intervals between frames k11 and k59. for an lt, normally it will not matter in which k2 frames the eoc data is written and read, as long the read/writes are done at 6 ms intervals (i.e., every 48 k2 frames). this is because there is no critical timing involved between the reception of an eoc message and its response, as there is at an nt. for an nt, ansi t1.601, section 8.3.2, speci?s that the eoc response must occur in the next available outgoing eoc frame. this means that the system has 13 k2 frames between the reception of a new eoc message at frame k95 (relative to rsf) and the transmission of the response to that message. thus, the eoc timing at the nt should be referenced to rsf. because of well- de?ed timing between rsf and tsf at the nt, there is no reason to use tsf for eoc timing. q38 : the data sheet states that adea = 0 and idea = 1 should not be used at the same time; why not? a38 : this mode is not recommended because it could result in a system-level problem. consider a typi- cal deactivation sequence for a network having a remote nt1 (i.e., an lt-to-nt connection with at least one intermediate element, as shown in ansi t1.601, figure e1) . the following table shows the events at the nt and lt when the lt initiates a deactivation. the lt uses adea in the case of an intermediate element to propagate the deactivation bit downstream without shutting itself down (as it would do if ldea were set instead): * this stores the coef?ients and prepares the transceiver for deactivation. deactivation will occur on loss of signal from the intermediate element. ? stores the coef?ients and deactivates the lt transmitter (stops transmitting). notice that adea = 0 and ldea = 1 are permitted at the last step. this is because the nt has already stored its coef?ients; however, if idea = 1 were set earlier (for example, in step 2), the lt might deactivate before the downstream elements had stored their coef?ients, and a clean deactivation would not occur. therefore, to help avoid turning off the lt before all the down- stream elements store their coef?ients, this state was de?ed as invalid. also, note that idea = 1 will cause a chip set in the lt mode to store coef?ients and deactivate, but it only causes a chip set in the nt mode to store coef?ients. deactivation at the nt only occurs upon loss of the u-interface signal. note : the preceding deactivation procedure is only an illustration. in a nonrepeater envi- ronment, step 2 could be adea = ldea = 1, which would cause the lt to automatically save its coef?ients and, within three or four k2 frames, deactivate. this case assumes that the nt has properly detected dea = 0 and then stored its coef? cients within those three or four frames. lt state lt k2 data in nt k2 data out nt action normal operation adea = 1 ldea = 0 dea = 1 downstream deactivate adea = 0 ldea = 0 dea = 0 set idea = 1 upon third consecutive dea = 0* after an appropriate amount of time to allow the message to propagate and the nt to react. lt deactivates ldea = 1 ? adea = 1 x detects loss of signal and deactivates
48 48 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) q39 : what is the relationship between istp and ldea? a39 : the istp bit should be set to 1 before or at the same time as ldea is set to 1. once the chip set is deactivated, setting istp to 0 for at least three k2 frames will initiate start-up. however, it is neces- sary for ldea to be 0 before time t7 (see ansi table 5, figure 16) for the start-up process to be successfully completed. q40 : when should nebes and febes be counted? a40 : during activation, nebes and febes will occur at each end of the link between the time framing is initially achieved and the time the link is fully operational at each end. these nebe/febe occurrences are normal and are of no interest. therefore, nebe/febe counters should be reset to zero after the link is fully operational. this is most easily achieved by delaying about 500 ms after getting oof = 1 and then resetting the nebe/febe counters. q41 : how is the d+ channel for 3-ds0 tdm applica- tions generated (bellcore tr-tsy-000397)? a41 : since the crc bits are not passed to the k2 inter- face, the d+ channel cannot be formed directly; those bits must be generated externally. also, a recent standard ballot addressed this issue by noting that, in general, the form of the d+ channel is application-dependent, so a broad standard is not being developed. q42 : how does rsf behave during a reframe? a42 : rsf behavior is transparent to the oof (out-of- frame) condition. whenever the chip thinks it has found an isw, it forces rsf high. rsf stays high for 12 k2 frames, at which point it goes low until the occurrence of the next isw. q43 : does the k2 f clock do anything strange when a reset is asserted? this clock is being used to initialize an elastic store, and it seems to be pro- ducing some strange glitches. a43 : there are two ways to reset the chip: 1. assert the reset pin low. 2. assert the k2 afrst bit (dc octet) high. the difference between these two resets is that #1 resets the entire chip, including the on-chip pll, while #2 resets everything except the pll. therefore, for both resets, the counter which con- trols the frequency gets loaded to its initial value, but the counter which controls the phase only gets reset when the reset pin is asserted. in the case described, this means that with either reset #1 or #2, the frequency counter controlling f will be reinitialized, which could cause a strange duty cycle on f for one clock period. but once this initialization occurs, the f clock immedi- ately starts behaving normally, even if the reset control remains active (also, in the case of reset #1, the pll starts to acquire). from a system standpoint, you can always count on f behaving predictably when reset is released because reset #1 or #2 must be asserted for at least 3 k2 frames, and the f clock duty cycle will stabilize after one k2 frame. so any logic for an elastic store which uses f should initialize upon exit from the reset state. however, be sure to consider the effect the shift in f may have on other parts of the system. q44 : what is the phase relationship between mtc and f at the lt? a44 : f is phase-locked to mtc by a second-order pll that has a ? db frequency of approximately 0.5 hz and has about 0.4 db of peaking.
lucent technologies inc. 49 data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) miscellaneous q45 : does the T7264 have a second source? a45 : it is manufactured at multiple lucent me loca- tions, but no second source outside lucent is currently available. q46 : are digital i/os ttl or cmos compatible? a46 : both. all i/os are cmos. they are speci?d at ttl because the current requirement makes this more dif?ult to meet. at higher output voltages, the current will be less, perhaps 100 ma at 3.5 v. q47 : what is the current sinking capability of osync? a47 : the osync lead supports a standard ttl load and will sink (or source) 1.6 ma. q48 : what are the tolerances of the various discrete components around the chip set? a48 : discrete components and their tolerances are as follows: q49 : if a switching power regulator is used in the system, is there a frequency to which it should be set? a49 : a switching frequency of 80 khz or higher multiples, synchronous to the 2b1q band clock, would be optimal. an 80 khz clock is available at pin 43 that is synchronous with the 2b1q signals. q50 : please explain how to use the ffc pin in detail and its purpose. a50 : the ffc pin can be used in applications where the mtc clock is switched from one source to another and may have glitches during the switch. one example of this is in dlc applications when the system switches to a protection clock board, and a new mtc clock is used. before the protec- tion switch, ffc should be brought low to freeze the internal states of the timing recovery circuitry. after the new clock has stabilized, ffc can be brought high again and the T7264 circuitry will lock to the new clock without dropping the u- interface. without the ffc function, the u-inter- face might be dropped while the new clock is being applied. q51 : what is the meaning of free-running and phase- locked in table 3 of this data sheet? a51 : in table 3, ckout is de?ed to be either 3-stated, 15.36 mhz free-running, 7.68 mhz free- running, or 10.24 mhz phase-locked. free-run- ning means that the ckout clock is directly derived from the 15.36 mhz crystal oscillator clock that is not synchronous with the u-interface line rate. phase-locked means that the 10.24 mhz ckout clock is synchronous with the u-interface line rate. this clock does not have 50% duty cycle, and will experience occasional duty-cycle adjustments (i.e., phase steps) to keep it synchronous with the u-interface. (see the note at the bottom of table 3 in the data sheet.) q52 : what are the ?ter characteristics of the pll at the nt? a52 : the ? db frequency is approximately 5 hz; peaking is about 1.2 db. q53 : is it possible to get a T7264-based lt to operate properly with a nt without supplying an mtc clock? a53 : yes. tying mtc to +5 v will yield a 100 ppm mtc, which a lucent nt will be able to lock to in most cases. this con?uration should be used for laboratory purposes only. for all serious perfor- mance testing, a 32 ppm (or better) mtc should be used. q54 : if there are several nt-mode T7264s on a board, can only one crystal be used to run them? a54 : yes. the following is an explanation of how this is accomplished (refer to table 3 on page 6 of this data sheet). first, connect a crystal in the normal fashion to one T7264; the v ddo , mclk, and cksel pins should be set per the ?st entry in table 3 (+5/0/0). now set the v ddo , mclk, and cksel pins on all the other T7264s as per the last entry in table 3 (0/15.36/1), and use the 15.36 mhz signal coming from ckout (pin 23) of the ?st T7264 to provide the 15.36 mhz input to mclk (pin 24) on the others. line-side resistors 16.9 w 7% dc blocking capacitor 1.0 m f 5% device-side resistors 16.9 w 1% bypass capacitors 0.1 m f 10% bypass capacitors 1.0 m f 10%
50 50 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) q55 : will the T7264 run in nt mode with the k2 clock slaved to an external backplane? a55 : the T7264 does not support this mode. for those applications where this is an issue, systems designers have generally provided some elastic store on the k2-to-backplane asic. the elastic store must be sized according to the amount of jitter which can be introduced into a system and the amount of jitter gain in the system aplls. for example, assume that the backplane clock is derived from a recovered t1 clock. the worst- case jitter for a t1 line is 0.259 ui at frequencies of 0.001 hz?0 hz. considering that an lt- mode T7264 apll has jitter peaking of 0.4 db at 0.15 hz, the 0.259 ui of jitter could be ampli?d to 0.271 ui. since 0.271 ui of 80 khz is 3.39 m s, this is how much elastic store is required. note that this is a simpli?d example: there may be other aplls in the system (for example, the t1-to-backplane clock apll), and their peaking must be factored in also. in addition, it is desirable to design in some margin. q56 : is there a recommended method for powering the T7264? for example, is it desirable to separate the power supplies, etc.? a56 : the T7264 is not extremely sensitive to power supply schemes. following standard practices of decoupling power supplies close to the chip and, if power and ground planes are not used, keeping power traces away from high-frequency signals, etc., should yield acceptable results. separating the T7264 analog power supplies from the digital power supplies near the chip can yield a small improvement, and the same holds true for using power and ground planes vs. discrete traces. note : if analog and digital power supplies are separated, the xtal power supply (v ddo ) should be tied to the digital supplies (v ddd ). q57 : what is the effect of ramping down the power supply voltage on the device? when will it provide a valid reset? this condition can occur when a line-powered nt1s line cord is repeatedly plugged in and removed and plugged in again before the power supply has had enough time to fully ramp up. a57 : the devices reset is more dependent on the reset pin than the power supply to the device. as long as the proper input conditions on the reset pin (see table 32) are met, the device will have a valid reset. note that this input is a schmitt-trigger input. q58 : does the output jitter of the 9 khz f clock on an nt-mode T7264 meet the 5% peak-to-peak jitter requirement described in itu-t i.430, section 8.3, assuming the s/t transceiver is the t7252a? a58 : yes, the 5% requirement applies to high- frequency jitter (>50 hz) at the nt. the T7264 produces approximately 100 ns of high-frequency jitter in the nt mode on f, and the t7252a can accept up to 160 ns of high-frequency jitter on its input clock and still meet the i.430 requirement. q59 : what should be known before having a T7264- based product conformance tested at bellcore? a59 : a copy of the bellcore test bed interface speci? cation should be obtained from bellcore to get the latest requirements. the bellcore speci?ation, when last reviewed by lucent, required that a unit under test provide access to the following signals or state indicators. (the T7264 pin name in upper case, or k2 bit name, lower case, which corresponds to the bellcore-required signal, is enclosed in braces.) transceiver status signals : fully operational state indicator {oof or osync} full reset state indicator {xact} loss-of-frame alignment (opt) {oof or osync} rx crc check indicator (opt) {nebe} transceiver control signals : transceiver full reset { reset } transceiver activation {istp} lt transceiver deactivation {ldea} transmit m1?4 bit control {k2 access} transmit 2b+d payload gating {received act} continuous scrambled output { iloss at nt} test mode {ipbk at lt} intertransceiver signals (lt only) : superframe timing {conditioned tsf} 2.56 mhz clock {ckout/4} note : T7264 must be optioned for a 10.24 mhz ckout. 2b+d test access 18-bit bursted clock and corresponding 2b+d serial data stream must be accessible in both transmit and receive directions.
lucent technologies inc. 51 data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) q60 : in the idle mode, when afrst or reset is active, the current increases from 6 ma (powerdown mode) to 40 ma?0 ma (normal mode). is this proper behavior for the T7264? also, is this a cor- rect interpretation of the data sheet description of idle mode (page 10, third paragraph)? a60 : this behavior is proper for the T7264. the reason more current is needed in the reset state (i.e., reset pin or afrst bit active) is that much of the analog circuitry (line driver, band gap voltage ref- erences, a/d, and d/a) is powered down during the idle state, but is active during the reset state. notice that idle and reset are two different states: reset state overrides idle when the reset pin or afrst is active. the reset state is normally a tran- sient state which only lasts a short time, unless the reset function is being constantly asserted. this means that reset should not be used indis- criminately as part of a general start-up proce- dure. the meaning of the third paragraph on page 10 in the data sheet is that at the end of a reset condition, the transceiver will change to the idle state (only momentarily if a start-up request is being made via the istp bit or a far-end wakeup tone). in this way, the data sheet is con- sistent with these results. q61 : can you provide detailed information on the active power consumption of the T7264? a61 : when discussing active power measurement ?ures, it is important to note that the conditions under which power measurements are made are not always completely stated by 2b1q integrated circuit vendors. for example, loop length is not typically mentioned in regard to power dissipa- tion, yet power dissipation on a short loop is noticeably greater than on a long loop. there are two reasons for the increased power dissipation at shorter loop lengths: 1. the overall loop impedance is smaller, requir- ing a higher current to drive the loop. 2. the far-end transceiver is closer, requiring the near-end transceiver to sink more far-end cur- rent in order to maintain virtual ground at its transmitter outputs. the lab measurements in the following table pro- vide examples of how power dissipation varies with loop length for a speci? T7264 with its 15.36 mhz ckout output enabled and driving 40 pf (see the next table below for information on ckout). note that power dissipation with a zero length loop (the worst-case loop) is about 35 mw higher than a loop of >3 kft length. thus, loop length needs to be considered when determining worst-case power numbers. * this is the con?uration used in method b discussed on the next page. also, in the case of the T7264, the use of the out- put clock ckout (pin 23) must be considered since its in?ence on power dissipation is signi? cant. some applications may make use of this clock, while others may leave it 3-stated. the power dissipation of ckout is as follows: the methods used to evaluate typical and worst- case power consumption are based on lucents commitment to provide its customers with accu- rate and reliable data. measurements are per- formed as part of the factory test procedure using automated test equipment. bench top tests are performed in actual isdn systems to correlate the automated test data with a typical implemen- tation. a conservative margin is then added to the test results for publication in the data sheets. loop con?uration power (mw) 18 kft/26 awg 273 6 kft/26 awg 273 3 kft/26 awg 277 2 kft/26 awg 280 1 kft/26 awg 288 0.5 kft/26 awg 296 0 kft 308 135 w load, iloss or lpbk active, no far-end transceiver* 281.5 ckout frequency (mhz) power due to ckout 40 pf load (mw) power due to ckout no load (mw) 15.36 21.3 11.0 10.24 17.7 9.1 7.68 12.6 6.6
52 52 lucent technologies inc. data sheet april 1998 T7264 u-interface 2b1q transceiver appendix a. questions and answers (continued) a61: (continued) the following tables provide power consumption data in several formats to allow customers to compare transceiver solutions. the three test condition categories re?cted in the tables have been designated method a, which re?cts T7264 data sheet measurements; method b, which re?cts data obtained with a method used by other vendors; and method c, which details revised T7264 measurements. method a * this is the worst-case loop. ? 3 mw should be added for 85 c. the test conditions re?cted in method b repre- sent a con?uration used by other silicon vendors which eliminates the far-end transceiver from the network. this con?uration should not be used to determine a system's total power requirements, but it can be used for comparison purposes among silicon solutions. method b * the transceiver under test must be in a local u-loopback mode. ? 3 mw should be added for 85 c. anticipated customer con?uration. the conditions and test results in method c are the product of recent investigations into the device's mature test data. they can be used to reliably determine system-level power consump- tion requirements. method c * this is the worst-case loop. ? 3 mw should be added for 85 c. anticipated customer con?uration. test condition value loop con?uration 0 kft* temperature 25 c ? power supply voltage 5 v ckout 15.36 mhz max. power consumption 350 mw test condition value loop con?uration 135 w load only* temperature 25 c ? power supply voltage 5 v ckout 3-stated max. power consumption 275 mw test condition value loop con?uration 0 kft* temperature 25 c ? power supply voltage 5 v ckout 3-stated max. power consumption 300 mw
data sheet april 1998 T7264 u-interface 2b1q transceiver lucent technologies inc. 53 appendix b. differences between the t-7264- - -ml, t-7264- - -ml2, and t-7264a- -ml devices technology the t-7264- - -ml device is a 0.9 m m cmos technology device, while the t-7264- - -ml2 and the t-7264a- -ml are 0.6 m m cmos technology devices. standard in 1996, the european telecommunications standards institute (etsi) added a microinterruption immunity require- ment to etr 080 (sections 5.4.5 and 6.2.5). section 5.4.5 in etsi etr 080 states the following: n a microinterruption is a temporary line interruption due to external mechanical activity on the copper wires con- stituting the transmission path. n the effect of a microinterruption on the transmission system can be a failure of the digital transmission link. n the objective of this requirement is that the presence of a microinterruption of speci?d maximum length shall not deactivate the system, and the system shall activate if it has deactivated due to longer interruption. section 6.2.5 in etsi etr 080 states the following: n a system shall tolerate a microinterruption up to t = 5 ms, when simulated with a repetition interval of t = 5 ms. since this is a new requirement, implementers were allowed until the end of 1997 to adhere to this requirement. the T7264 device was upgraded to fully comply with this standard and the device was given an a suf? (T7264a). a proposal was added to the living list (which is intended to collect issues and observations for a possible future update of etsi etr 080) to change the value of the microinterruption requirement from 5 ms to 10 ms. the current T7264a device from lucent technologies microelectronics group meets and exceeds this new requirement. the above change to the transceiver has been fully veri?d, and test reports are available upon request.
lucen t t echnologies inc . rese r v es the r ight to ma k e changes to the product(s) or in f o r mation contained herein without notic e . no liability is assumed as a result of their use or application . no r ights under a n y patent accompa n y the sale of a n y such product(s) or in f o r mation. co p y r ight ?1998 lucen t t echnologies inc. all rights rese r v ed ap r il 1998 ds97-413isdn (replaces ds90-184smo s , a y93-032tcom, an d tn93-003tcom) for additional information, contact your microelectronics group account manager or the following: interne t : http://ww w .lucent.com/mic r o e-mail: docmaster@mic r o.lucent.com n . america: microelectronics grou p , lucen t t echnologies inc., 555 union boul e v ard, room 30l-15p-ba, allent o wn, p a 18103 1-800-372-2447 , f ax 610-712-4106 (in cana d a : 1-800-553-2448 , f ax 610-712-4106) asia p a cific : microelectronics grou p , lucen t t echnologies singapore pt e . ltd., 77 science p a r k d r i v e , #03-18 cintech iii, singapore 118256 t el . (65) 778 8833 , f ax (65) 777 7495 china: microelectronics grou p , lucen t t echnologies (china) c o ., ltd., a-f2, 23/ f , zao f ong uni v erse building, 1800 zhong shan xi road, shanghai 200233 p . r . chin a t el . (86) 21 6440 0468 , e xt . 316 , f ax (86) 21 6440 0652 j a p an: microelectronics grou p , lucen t t echnologies j apan ltd., 7-18, higashi-gotanda 2-chom e , shinag a w a-ku , t ok y o 141, j apan t el . (81) 3 5421 1600 , f ax (81) 3 5421 1700 eu r ope: data requests : mic r oelect r onics g r oup d at aline : t el . (44) 1189 324 299 , f ax (44) 1189 328 148 t echnical inqui r ies : german y : (49) 89 95086 0 (munich), united kingdom : (44) 1344 865 900 (bra c knell), france : (33) 1 41 45 77 0 0 (paris), sweden : (46) 8 600 7070 (sto c kholm), finland : (358) 9 4354 2800 (helsinki), i t a l y : (39) 2 6601 1800 (milan), s p ain : (34) 1 807 1441 (mad r id)

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